Patents by Inventor Yen-Huei Chen
Yen-Huei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144997Abstract: A semiconductor device includes a first memory array, a first bit line, a second memory array, a second bit line, a first conductive line and a first control circuit. The first bit line crosses over and is coupled to the first memory array, and extends along a first direction. The second bit line crosses over the second memory array, and is coupled to the first bit line. The first conductive line crosses over the second memory array and a part of the first memory array, and is configured to operate as a part of a first capacitor. The first control circuit is configured to couple the first conductive line to the second bit line when the first memory array is written.Type: ApplicationFiled: March 24, 2023Publication date: May 2, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Venkateswara Reddy KONUDULA, Teja MASINA, Nikhil PURI, Yen-Huei CHEN, Hung-Jen LIAO
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Publication number: 20240145385Abstract: A memory device includes a plurality of memory cells disposed over a substrate and formed as an array that has a plurality of rows and a plurality of columns. Each of the plurality of memory cells includes a plurality of transistors. A first subset of the plurality of memory cells, that are disposed in first neighboring ones of the plurality of rows, are physically coupled to a corresponding one of a plurality of second interconnect structures that carries a supply voltage through a corresponding one of a plurality of first interconnect structures. The plurality of first interconnect structures extend along a first lateral direction in parallel with a lengthwise direction of a channel of each of the transistors of the memory cells, and the plurality of second interconnect structures, disposed above the plurality of first interconnect structures, extend along a second lateral direction perpendicular to the first lateral direction.Type: ApplicationFiled: February 16, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
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Patent number: 11961554Abstract: A device includes a first power rail for a first power domain and a second power rail for a second power domain. A first circuit block is connected to the first power rail and a second circuit block is connected to the second power rail. The first and second circuit blocks are both connected to a virtual VSS terminal. A footer circuit is connected between the virtual VSS terminal and a ground terminal, and the footer circuit is configured to selectively control a connection between the virtual VSS terminal and the ground terminal.Type: GrantFiled: December 11, 2020Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Kao-Cheng Lin, Wei Min Chan, Yen-Huei Chen
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Patent number: 11963348Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.Type: GrantFiled: August 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen
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Patent number: 11948627Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.Type: GrantFiled: August 9, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao
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Publication number: 20240105241Abstract: Disclosed herein are related to a memory device. In one aspect, a memory device includes a set of memory cells. In one aspect, the memory device includes a first bit line extending along a direction. The first bit line may be coupled to a subset of the set of memory cells disposed along the direction. In one aspect, the memory device includes a second bit line extending along the direction. In one aspect, the memory device includes a switch coupled between the first bit line and the second bit line.Type: ApplicationFiled: February 16, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Yen-Huei Chen
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Patent number: 11929116Abstract: A memory device and a method for operating the memory device are provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.Type: GrantFiled: January 23, 2023Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
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Publication number: 20240079052Abstract: A semiconductor device includes a first memory bank, a second memory bank and a first write driver. The first memory bank is coupled to a plurality of first data lines, and configured to operate according to a first data signal. The second memory bank is configured to operate according to the first data signal. The first write driver is disposed between the first memory bank and the second memory bank, and configured to adjust a voltage level of one of the plurality of first data lines when the first memory bank is written according to the first data signal.Type: ApplicationFiled: March 24, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nikhil PURI, Venkateswara Reddy KONUDULA, Teja MASINA, Yen-Huei CHEN, Hung-Jen LIAO, Hidehiro FUJIWARA
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Publication number: 20240055048Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.Type: ApplicationFiled: July 31, 2023Publication date: February 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
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Publication number: 20240046979Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells being coupled correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including local write drivers correspondingly coupled to the segments; and a global write driver coupled to each of the local write drivers.Type: ApplicationFiled: October 6, 2023Publication date: February 8, 2024Inventors: Hidehiro FUJIWARA, Hung-Jen LIAO, Li-Wen WANG, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN
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Publication number: 20240046969Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.Type: ApplicationFiled: August 5, 2022Publication date: February 8, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Sheng WANG, Kao-Cheng LIN, Yangsyu LIN, Yen-Huei CHEN, Cheng Hung LEE, Jonathan Tsung-Yung CHANG
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Publication number: 20240029769Abstract: Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.Type: ApplicationFiled: July 26, 2023Publication date: January 25, 2024Inventors: Wei-Cheng Wu, Kao-Cheng Lin, Chih-Cheng Yu, Pei-Yuan Li, Chien-Chen Lin, Wei Min Chan, Yen-Huei Chen
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Publication number: 20240028254Abstract: A charge sharing scheme is used to mitigate the variations in cell currents in order to achieve higher accuracy for CIM computing. In some embodiments, a capacitor is associated with each SRAM cell, and the capacitors associated with all SRAM cells in a column are included in averaging the RBL current. In some embodiments, a memory unit associated to an RBL in a CIM device includes a storage element adapted to store a weight, a first switch device connected to the storage element and adapted to be controlled by an input signal and generate a product signal having a magnitude indicative of the product of the input signal and the stored weight. The memory unit further includes a capacitor adapted to receive the product signal and store an amount of charge corresponding to the magnitude of the product signal. The memory unit further include a second switch device adapted to transfer the charge on the capacitor to the RBL.Type: ApplicationFiled: July 31, 2023Publication date: January 25, 2024Inventors: Jonathan Tsung-Yung CHANG, Hidehiro FUJIWARA, Hung-Jen LIAO, Yen-Huei CHEN, Yih WANG, Haruki MORI
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Publication number: 20240021240Abstract: A memory array is disclosed. The memory array includes a plurality of memory cells disposed over a substrate. Each of the memory cells is coupled to a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit line pairs. First four of the memory cells that are coupled to four consecutive ones of the word lines and to a first one of the bit line pairs are abutted to one another on the substrate along a single lateral direction.Type: ApplicationFiled: July 12, 2022Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
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Publication number: 20230418557Abstract: A circuit includes a multiplier circuit that receives a signed mantissa of each data element of pluralities of input and weight data elements and generates two's complement products by performing multiplication and reformatting operations on some or all of the input data element signed mantissas and some or all of the weight data element signed mantissas, a summing circuit that receives an exponent of each data element of the pluralities of input and weight data elements and generates sums by adding each input data element exponent to each weight data element exponent, a shifting circuit that shifts each product by an amount equal to a difference between a corresponding sum and a maximum sum, and an adder tree that generates a mantissa sum from the shifted products.Type: ApplicationFiled: January 20, 2023Publication date: December 28, 2023Inventors: Chia-Fu LEE, Cheng Han LU, Yu-Der CHIH, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN, Chen-En LEE, Wei-Chang ZHAO, Haruki MORI, Hidehiro FUJIWARA
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Patent number: 11854943Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.Type: GrantFiled: January 12, 2023Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITEDInventors: Hidehiro Fujiwara, Tze-Chiang Huang, Hong-Chen Cheng, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yun-Han Lee, Lee-Chung Lu
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Publication number: 20230410851Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.Type: ApplicationFiled: July 31, 2023Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haruki MORI, Chien-Chi TIEN, Chia-En HUANG, Hidehiro FUJIWARA, Yen-Huei CHEN, Feng-Lun CHEN
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Publication number: 20230395160Abstract: A memory circuit includes first and second memory segments coupled to first and second write lines, and first and second write line circuits coupled to the first and second write lines and configured to receive first and second data signals. The first and second data signals have complementary low and high logical states during a write operation to the first or second memory segment, and each of the first and second data signals has the low logical state during a masked write operation to the first or second memory segment. The first and second write line circuits output, to the first and second write lines, first and second write line signals responsive to the first and second data signals during the write operation and float the first and second data lines during the masked write operation.Type: ApplicationFiled: July 31, 2023Publication date: December 7, 2023Inventors: Manish ARORA, Yen-Huei CHEN, Hung-Jen LIAO, Nikhil PURI, Yu-Hao HSU
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Publication number: 20230395143Abstract: A method of performing an in-memory computation includes storing a first subset of data in a first segment of a first memory array and a second subset of the data in a second segment of the first memory array, latching a first data bit from a first column of memory cells in the first segment of the first memory array, sequentially reading a plurality of second data bits from a second column of memory cells in the second segment of the first memory array, and performing a logic operation on each combination of the latched first data bit and each second data bit.Type: ApplicationFiled: August 10, 2023Publication date: December 7, 2023Inventors: Yen-Huei CHEN, Hidehiro FUJIWARA, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG
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Patent number: 11830544Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.Type: GrantFiled: July 15, 2022Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao