Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: A device disclosed includes first and second rows of memory cells, a first data line, and a first continuous data line. The first and second rows of memory cells are arranged in a first sub-bank and a second sub-bank, separated from the first sub-bank, respectively. The first data line is arranged across the first sub-bank and coupled to a first memory cell in the first row of memory cells. The first continuous data line includes a first portion arranged across the first sub-bank and a second portion arranged across the second sub-bank. The first continuous data line is coupled to a second memory cell in the second row of memory cells. The first portion of the first continuous data line is disposed in a first metal layer. The first data line and the second portion of the first continuous data line are in a second metal layer.

Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).

Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.

Abstract: A device includes a diode circuit. The diode circuit is coupled between a first input/output (I/O) pin and a second I/O pin of a circuit, and is configured to be turned off. The diode circuit is configured to provide a first discharging path for the first I/O pin of the circuit and a second discharging path for the second I/O pin of the circuit. The diode circuit includes a first transistor and a second transistor. The first transistor is between a node and the first I/O pin. The second transistor is between the node and the second I/O pin. The node is configured to receive a first voltage, and control terminals of the first transistor and the second transistor are configured to receive a second voltage. A voltage difference between the first voltage and the second voltage is configured to turn off the first transistor and the second transistor.

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.

Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.

Abstract: A memory circuit includes a first memory array including first memory cells wherein a plurality of first word lines is coupled with a plurality of rows of first memory cells in a first segment of the first memory array, and a plurality of second word lines is coupled with the plurality of rows of first memory cells in a second segment of the first memory array. The memory circuit also includes a read circuit configured to retrieve data from the first memory cells of the first memory array and a computation circuit configured to perform a matrix computation by combining first data retrieved from the first memory cells of the first segment with second data retrieved from the first memory cells of the second segment.

Abstract: A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.

Abstract: An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.

Abstract: The disclosed write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: A method of fabricating (a distributed write driving arrangement for a semiconductor memory device) includes: forming bit cells and a local write driver in a first device layer; forming a local write bit (LWB) line and a local write bit_bar (LWB_bar) line in a first metallization layer; connecting each of the bit cells correspondingly between the LWB and LWB_bar lines; connecting the local write driver to the LWB line and the LWB_bar line; forming a global write bit (GWB) line and a global write bit_bar (GWBL_bar) line in a second metallization layer; connecting the GWB line to the LWB line; connecting the GWB line and the GWBL_bar line to the corresponding LWB line and LWB_bar line; forming a global write driver in a second device layer; and connecting the global write driver to the GWB line and the GWBL_bar line.

Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.

Abstract: The disclosure introduces a write assist scheme that boost the word line of a selected memory cell by using a parasitic capacitor element coupled between the word line and a bit line of at least one unselected memory cell. The SRAM includes a word line, a first bit line, a second bit line, a first memory cell coupled to the first bit line and the word line, a second memory cell coupled to the second bit line and the word line, and a write assist circuit coupled to the second bit line. The write assist circuit is configured to clamp the second bit line to the word line during a write operation of the first memory cell.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.

Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.