Patents by Inventor Yen-Ming Chen

Yen-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901408
    Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sai-Hooi Yeong, Feng-Cheng Yang, Yih-Ann Lin, Yen-Ming Chen
  • Patent number: 11894421
    Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.V
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Yen-Ming Chen, Feng-Cheng Yang
  • Patent number: 11862713
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11862712
    Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Chung-Chi Wen, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11854688
    Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH3).
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11855207
    Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Jen Lai, Yen-Ming Chen, Tsung-Lin Lee
  • Patent number: 11855097
    Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu Lai, Kai-Hsuan Lee, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11856743
    Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11855022
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20230411220
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.
    Type: Application
    Filed: July 24, 2023
    Publication date: December 21, 2023
    Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Cheng Hong Yang, Shih-Hao Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11848230
    Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzung-Yi Tsai, Tsung-Lin Lee, Yen-Ming Chen
  • Publication number: 20230402428
    Abstract: A method includes attaching a wafer to a wafer chuck having a curved surface. The method further includes placing a device die on the wafer, such that a first dielectric layer of the device die is in contact with a second dielectric layer of the wafer, and performing an annealing process to bond the first dielectric layer to the second dielectric layer. The method further includes encapsulating the device die with an encapsulating material, forming redistribution lines overlapping the encapsulating material and the device die, and sawing the encapsulating material to form a plurality of packages.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chih Chiou, Yung-Chi Lin, Yen-Ming Chen
  • Publication number: 20230389447
    Abstract: A method of forming a semiconductor device includes providing a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Tsung-Chieh Hsiao, Po-Sheng Lu, Wei-Chih Wen, Liang-Wei Wang, Yu-Jen Wang, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20230387247
    Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: Wei-Yang Lee, Feng-Cheng Yang, Chung-Te Lin, Yen-Ming Chen
  • Publication number: 20230387183
    Abstract: Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 30, 2023
    Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20230386940
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming an interconnect structure, and forming a conductive feature electrically connected to the interconnect structure. The method also includes forming a first passivation layer over the interconnect structure and the conductive feature, and etching the first passivation layer to form an opening that exposes the conductive feature. The method further includes performing an electrical test on the conductive feature, filling the opening with an oxide material, and attaching a carrier substrate over the oxide material using a bonding layer.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Yang, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20230389256
    Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20230387305
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Chia-Ta Yu, Yen-Chieh Huang, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20230387269
    Abstract: A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 30, 2023
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Patent number: 11830922
    Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Feng-Cheng Yang, Chung-Te Lin, Yen-Ming Chen