Patents by Inventor Yen-Ming Chen

Yen-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor Device With Air-Gap Spacers
    Publication number: 20230068664
    Abstract: A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Kai-Hsuan Lee, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Yen-Ming Chen
  • INTEGRATED CIRCUIT DEVICE WITH IMPROVED RELIABILITY
    Publication number: 20230063857
    Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
  • Semiconductor Device With Funnel Shape Spacer And Methods Of Forming The Same
    Publication number: 20230052380
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.
    Type: Application
    Filed: October 31, 2022
    Publication date: February 16, 2023
    Inventors: Cheng-Yu Yang, Yen-Ting Chen, Wei-Yang Lee, Fu-Kai Yang, Yen-Ming Chen
  • Fin field effect transistor (FinFET) device structure with dummy Fin structure
    Patent number: 11569130
    Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Chih-Chieh Yeh
  • Method for forming semiconductor device structure with cap layer
    Patent number: 11569386
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extended above a substrate, and a first source/drain structure formed over the first fin structure. The first source/drain structure is made of an N-type conductivity material. The semiconductor device structure also includes a second source/drain structure formed over the second fin structure, and the second source/drain structure is made of an P-type conductivity material. The semiconductor device structure also includes a cap layer formed over the first source/drain structure, wherein the cap layer is made of P-type conductivity material.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Replacement gate process for FinFET
    Patent number: 11569236
    Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen
  • Nanostructures and method for manufacturing the same
    Patent number: 11538927
    Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes forming a stack of a first type and a second type epitaxial layers on a frontside of a semiconductor substrate, patterning the stack to form a fin-shaped structure, depositing a dielectric layer on sidewalls of the fin-shaped structure, and recessing the dielectric layer to expose a top portion of the fin-shaped structure. A top surface of the recessed dielectric layer is above a bottom surface of the stack. The exemplary manufacturing method also includes forming a gate structure over the top portion of the fin-shaped structure, etching the semiconductor substrate from a backside of the semiconductor substrate, and etching at least a bottommost first type epitaxial layer and a bottommost second type epitaxial layer through the trench.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: December 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Yen-Ming Chen, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng
  • Stress reduction structure for metal-insulator-metal capacitors
    Patent number: 11532695
    Abstract: A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices. The device may further include a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In addition, the device may further include a second passivation layer disposed over the MIM capacitor structure. In various examples, a stress-reduction feature is embedded within the second passivation layer. In some embodiments, the stress-reduction feature includes a first nitrogen-containing layer, an oxygen-containing layer disposed over the first nitrogen-containing layer, and a second nitrogen-containing layer disposed over the oxygen containing layer.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Mu Yin, Hung-Chao Kao, Hsiang-Ku Shen, Dian-Hau Chen, Yen-Ming Chen
  • ACTIVE REGION PATTERNING
    Publication number: 20220392897
    Abstract: Semiconductor structures and fabrication processes are provided. A semiconductor according to the present disclosure includes a first region including a first fin, a second fin, and a third fin extending along a first direction, and a second region abutting the first region. The second region includes a fourth fin and a fifth fin extending along the first direction. The first fin is aligned with the fourth fin and the second fin is aligned with the fifth fin. The third fin terminates at an interface between the first region and the second region.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 8, 2022
    Inventors: Chih-Hsin Yang, Yen-Ming Chen, Dian-Hau Chen
  • FINFET STRUCTURE AND METHOD WITH REDUCED FIN BUCKLING
    Publication number: 20220384650
    Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
    Type: Application
    Filed: July 28, 2022
    Publication date: December 1, 2022
    Inventors: Wei-Jen LAI, Yen-Ming CHEN, Tsung-Lin LEE
  • AIR GAP FORMATION BETWEEN GATE SPACER AND EPITAXY STRUCTURE
    Publication number: 20220384442
    Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu LAI, Kai-Hsuan LEE, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
  • EPITAXIAL FEATURES OF SEMICONDUCTOR DEVICES
    Publication number: 20220384654
    Abstract: Methods and devices formed thereof that include a fin structure extending from a substrate and a gate structure is formed over the fin structure. An epitaxial feature is formed over the fin structure adjacent the gate structure. The epitaxial feature can include a hollow region (or dielectric filled hollow region) in the epitaxial source/drain region. A selective etching process is performed to remove at least a portion of an epitaxial region having a second dopant type to form the hollow area between the first epitaxial portion and the third epitaxial portion.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Feng-Ching CHU, Wei-Yang LEE, Feng-Cheng YANG, Yen-Ming CHEN
  • Multi-Layer High-K Gate Dielectric Structure
    Publication number: 20220384454
    Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
  • MRAM STRUCTURE FOR BALANCED LOADING
    Publication number: 20220384712
    Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
  • Conformal Transfer Doping Method for Fin-Like Field Effect Transistor
    Publication number: 20220376090
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 24, 2022
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • SEMICONDUCTOR DEVICE STRUCTURE
    Publication number: 20220376079
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
  • Air spacer for a gate structure of a transistor
    Patent number: 11508827
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiu Liu, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen
  • Method for forming different types of devices
    Patent number: 11508736
    Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • METHOD OF FORMING A STRESS REDUCTION STRUCTURE FOR METAL-INSULATOR-METAL CAPACITORS
    Publication number: 20220367605
    Abstract: A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices. The device may further include a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In addition, the device may further include a second passivation layer disposed over the MIM capacitor structure. In various examples, a stress-reduction feature is embedded within the second passivation layer. In some embodiments, the stress-reduction feature includes a first nitrogen-containing layer, an oxygen-containing layer disposed over the first nitrogen-containing layer, and a second nitrogen-containing layer disposed over the oxygen containing layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Jin-Mu YIN, Hung-Chao KAO, Hsiang-Ku SHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • FIN ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES
    Publication number: 20220367288
    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHIANG, Chih-Hao Wang, Kuan-Lun Cheng, Yen-Ming Chen