Patents by Inventor Yi-An Chien

Yi-An Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11895192
    Abstract: A wrapper layer over a target interface receives requests from client devices over a different interface, converts the requests into a format that is compatible with the target interface, and transmits each converted request over the target interface for processing by a service. The wrapper layer also processes a request by a client device to subscribe to a certain type of update made via the target interface by verifying that the client device is authorized to access a resource associated with that type of update and creating a subscription that identifies the client device and the type of update. When the wrapper layer subsequently receives a request corresponding to that type of update, the wrapper layer matches attributes of the request to the subscription by the client device and transmits a message notifying the client device of the request.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: February 6, 2024
    Assignee: SPLUNK INC.
    Inventors: Neel Mehta, Allyson Aberg, Joel Jacob, William Huang, Neha Kumari, Yi Chien Lee, Anthony Ng, Rodrigo Paulo Quaresma, Qi Shu, Warren Shum, Jonathan Yeung
  • Patent number: 11862080
    Abstract: A display panel with a less costly backup arrangement for failed light-emitting elements and a driving method thereof are disclosed. The display panel includes a plurality of pixels. Each pixel includes a plurality of main sub-pixels and a backup sub-pixel. For any one of the pixels, if there is a failed main sub-pixel, the backup sub-pixel is activated and configured for cooperating with non-failed main sub-pixels to output metamerized light of a desired target color in order that no change in color or brightness is perceived by a viewer.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: January 2, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Te-En Tseng, Tsai-Yi Chien
  • Patent number: 11837995
    Abstract: A one-coil multi-core inductor-capacitor (LC) oscillator is provided. The one-coil multi-core LC oscillator includes a main coil and at least one mode suppression device. The main coil includes an outer wire and a central wire, wherein the outer wire is coupled to a first core circuit and a second core circuit, and the central wire is coupled between a first node and a second node of the outer wire. More particularly, an outer loop formed by the outer wire corresponds to a first mode of the one-coil multi-core LC oscillator, and inner loops formed by the outer wire and the central wire correspond to a second mode of the one-coil multi-core LC oscillator, where the at least one mode suppression device is configured to suppress one of the first mode and the second mode.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: December 5, 2023
    Assignee: MEDIATEK INC.
    Inventors: Hao-Wei Huang, Song-Yu Yang, Ang-Sheng Lin, Yi-Chien Tsai
  • Patent number: 11824938
    Abstract: Described herein are techniques for integrating external sensors to an edge device, such as for ingesting data into a data intake and query system. The edge device has an internal message broker for communicating with internal (e.g., preconfigured, recognized) sensors, and an external message broker for communicating with external (e.g., customer-configured, otherwise unrecognized) sensors. The external message broker provides access to customer configuration of external sensors, but is logically quarantined from the internal message broker to prevent unwanted customer access to internal configurations. The internal and external message brokers interface only via a bridging service that transforms external sensor data into data based on customer-configurable transformations. The transformed data can be handled by the edge device and/or downstream components (e.g., a data intake and query system) in the same manner as internal sensor data.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: November 21, 2023
    Assignee: SPLUNK Inc.
    Inventors: Rodrigo Paulo Quaresma, Neel Mehta, Warren Shum, William Huang, Jonathan Yeung, Yi Chien Lee, Masrur Mahmood, Anthony Ng, Allyson Aberg, Qi Shu, Neha Kumari, Joel Jacob
  • Publication number: 20230365395
    Abstract: The present disclosure provides a structure and method of fabricating the structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Yuan-Chih Hsieh, Hsing-Lien Lin, Jung-Huei Peng, Yi-Chien Wu
  • Publication number: 20230360976
    Abstract: Various embodiments of the present disclosure are directed towards a method for nondestructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee
  • Patent number: 11804335
    Abstract: A power storage device has a first power storage unit, a second power storage unit, a third power storage unit, and a fourth power storage unit. The power storage device is provided with a common electrode being integrated molding to make the first power storage unit and the second power storage unit connected in series, the third power storage unit and the fourth power storage unit connected in series, the first power storage unit and the third power storage unit connected in parallel, and the second power storage unit and the fourth power storage unit connected in parallel, so inside of the power storage device can have high potential and high capacitance, and avoid the problem of increasing the overall impedance caused by the conventional welding process. Further, the power storage device uses both surfaces of the common electrode at the same time to save electrode material.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: October 31, 2023
    Assignee: WAYS TECHNICAL CORP., LTD.
    Inventors: Wen-Hsien Ho, Pei-Yi Chien
  • Patent number: 11789282
    Abstract: A projection apparatus including an illumination system and a projection imaging system is provided. The illumination system is adapted to emit an illumination beam, and the illumination system includes a light source module and a light shaping module. The light source module is adapted to emit at least one beam. The light shaping module is disposed on the transmission path of the at least one beam. The at least one beam forms an illumination beam after passing through the light shaping module, and the illumination beam has a light imaging matching angle. The light shaping module includes at least one first lens element. The at least one first lens element is disposed on the transmission path of the at least one beam. The projection imaging system is disposed on a transmission path of the illumination beam. The projection apparatus is suitable for eliminating stray light and crosstalk of images.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: October 17, 2023
    Assignee: Coretronic Corporation
    Inventor: Yi-Chien Lo
  • Publication number: 20230317753
    Abstract: Optical modules and methods of forming the same are provided. In an embodiment, an exemplary method includes forming multiple first optical elements over a first wafer, forming multiple second optical elements over a second wafer, forming multiple third optical elements over a third wafer, aligning the first wafer with the second wafer such that, upon the aligning of the first wafer with the second wafer, each first optical element is vertically overlapped with a corresponding second optical element. The method also includes bonding the first wafer with the second wafer to form a first bonded structure, aligning the second wafer with the third wafer such that, and upon bonding the second wafer of the first bonded structure to the third wafer, where upon the aligning of the second wafer with the third wafer, each second optical element is vertically overlapped with a corresponding third optical element.
    Type: Application
    Filed: August 31, 2022
    Publication date: October 5, 2023
    Inventors: Jung-Huei Peng, Chun-Wen Cheng, Yi-Chien Wu
  • Patent number: 11767216
    Abstract: The present disclosure provides a structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yuan-Chih Hsieh, Hsing-Lien Lin, Jung-Huei Peng, Yi-Chien Wu
  • Patent number: 11746047
    Abstract: A wired and detachable, moveable, dis-assemble, re-assemble USB or Wireless charging-unit(s) which has minimum feet DC power delivery wire that is manual to coil, wrap within unit's own space for wire-arrangement, said each wired and detachable unit(s) cover broad area and people can chare external product(s) at any location within said area; wherein said unit(s) assembly with electric product which is at least one (1) desk, floor, wall-mounted item, light, (2) power strip, (3) selfie LED light has built-in or added-on image capture device(s).
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: September 5, 2023
    Inventors: Tseng-Lu Chien, De-Yi Chien, De-Ying Cian
  • Patent number: 11751392
    Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stack
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: September 5, 2023
    Assignee: SunRise Memory Corporation
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Chien
  • Patent number: 11749569
    Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee
  • Patent number: 11749024
    Abstract: The present invention provides a graphics processing method and an eye-tracking system capable of providing adaptive foveated rendering. If the system latency of a current application is greater than the threshold latency under the existing rendering parameter, adjusted rendering parameters are provided by adjusting the existing rendering parameters according to the system latency of the current application. Foveated images may thus be generated according to the adjusted rendering parameters in order to maintain the balance of resolution quality and rendering performance.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: September 5, 2023
    Assignee: Ganzin Technology, Inc.
    Inventors: Kuei-An Li, Shao-Yi Chien
  • Patent number: 11734743
    Abstract: A system comprising a computer-readable storage medium storing at least one program, and a computer-implemented method for enhancing and personalizing an interactive marketplace. The systems and methods provided herein may allow a user to receive search results that are tailored to the user's personal preferences based on social and purchasing information known about the user. In addition, the systems and methods provided herein may provide shipping updates to a buyer that include a personalized message based on location information provided by the package being shipped. In addition, the systems and methods provided herein allow merchants to provide incentives and rewards for shoppers by participating in interactive shopping games.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: August 22, 2023
    Assignee: EBAY INC.
    Inventors: Michael George Lenahan, Ben Lucas Mitchell, Chahn Chung, Myra Sandoval, Timothy Sean Suglian, Matthew Bret MacLaurin, James Ross Skorupski, Jesse Wolfe, Hsin-Yi Chien, Marie Jeanette Floyd Tahir, Jai Dandekar, Healey Cypher
  • Publication number: 20230262026
    Abstract: A data transmission system and method thereof for edge computing are provided. A terminal mobile station international subscriber directory number (MSISDN) and a terminal IP of a target terminal are obtained with a domain name system (DNS) by a device providing communication services from the data transmission system. After data packets are sent to the data transmission system, if the target terminal is in an idle mode, a paging message is sent by a terminal wake-up module to enable the target terminal to return to a connected mode for communication. Before a connection is established between the data transmission system and the target terminal, downlink data packets can be temporarily stored, and the packets can be sent after the target terminal is in the connected mode. A computer readable medium for executing the data transmission method is also provided.
    Type: Application
    Filed: January 9, 2023
    Publication date: August 17, 2023
    Inventors: Yi-Hua WU, Wei-Shan LU, Kang-Hao LO, Cheng-Yi CHIEN, Yueh-Feng LI, Ling-Chih KAO
  • Patent number: 11726564
    Abstract: An optical system includes an eye-tracker and a head-mounted display for providing accurate eye-tracking in interactive virtual environment. The eye-tracker includes a sensor module captures one or multiple eye images of a user. The head-mounted display includes a processor and a display for presenting the user interface. The processor provides a user interface which includes one or multiple UI elements based on one or multiple gaze points of the user which are computed based on the one or multiple eye images, acquires the distance between an estimated gaze point of the user and each UI element, acquires the score of each UI element based on the distance between the estimated gaze point and each UI element, and sets a specific UI element with a highest score as the target UI element associated with the estimated gaze point of the user.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: August 15, 2023
    Assignee: Ganzin Technology, Inc.
    Inventors: Kuan-Ling Liu, Po-Jung Chiu, Yi-Heng Wu, Kuei-An Li, Shao-Yi Chien
  • Patent number: 11726465
    Abstract: A semiconductor fabrication facility (FAB) is provided. The FAB includes a group of processing tools. The FAB also includes a number of sampling tubes connecting the group of processing tools. In addition, the FAB includes a sampling station which includes a connection port, a valve manifold box and a controller. The valve manifold box is used for switching a gas sample from one of the processing tools to the connection port. The controller is sued for controlling the connection of the valve manifold box and the sampling tubes. The FAB further includes a metrology module. The metrology module is connected to the connection port of the sampling station and is used to perform a measurement of a parameter related to the gas sample.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Lee-Chun Chen, Yi-Chien Yang, Chia-Lin Hsu
  • Patent number: 11730000
    Abstract: A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: August 15, 2023
    Assignee: SunRise Memory Corporation
    Inventors: Eli Harari, Wu-Yi Chien
  • Patent number: D991975
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: July 11, 2023
    Assignee: Microsoft Corporation
    Inventors: Joseph Wheeler, Yi-An Chien, Joann Marie Maisonet