Patents by Inventor Yi-An Chien

Yi-An Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11327335
    Abstract: A display apparatus includes a display device and an optical element. The display device is configured to project an image beam to a first diaphragm. The optical element is disposed on the transmission path of the image beam. The optical element includes a second diaphragm, the second diaphragm is located on one side of the first diaphragm, and the first diaphragm is located between the second diaphragm and the display device. The area of the second diaphragm approximates the area of the first diaphragm. The image beam passes through the first diaphragm and the second diaphragm and is projected to a projection target.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: May 10, 2022
    Assignee: Coretronic Corporation
    Inventors: Yi-Chien Lo, Hsin-Hsiang Lo, Chuan-Chung Chang, Fu-Ming Chuang
  • Publication number: 20220136155
    Abstract: Aspects herein are directed to a composite nonwoven textile suitable for use in apparel and other articles that are resistant to pilling. The composite nonwoven textile may be finished by one or more of applying a chemical binder to a first face of the composite nonwoven textile and forming thermal bonding sites. The chemical binder and the thermal bonding sites help to secure fiber terminal ends and minimize the formation of pills.
    Type: Application
    Filed: October 26, 2021
    Publication date: May 5, 2022
    Inventor: Ching-Yi Chien
  • Patent number: 11317800
    Abstract: A method of monitoring eye strain includes detecting the blink status, the vergence status and the pupil status of a user, and then determining whether the user encounters eye strain according to at least one of the blink status, the vergence status and the pupil status of the user. The method further includes facilitating the user to blink or informing the user of eye strain.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 3, 2022
    Assignee: Ganzin Technology, Inc.
    Inventors: Kuei-An Li, Su-Ling Yeh, Shao-Yi Chien
  • Patent number: 11314158
    Abstract: A microelectromechanical apparatus includes a substrate, a light diffuser device, a plurality of actuator devices, and a controller. The light diffuser device is disposed on the substrate. The actuator devices surround the substrate and are coupled to the substrate. The controller is coupled to the actuator devices. The controller applies a voltage to at least one of the actuator devices to drive the substrate and to control the light diffuser device to actuate according to a reference axis perpendicular to the light diffuser device. A projection apparatus is also provided. In the disclosure, a motion pattern and motion complexity of the light diffuser device may be enhanced. Enhancement of the movement pattern and movement complexity may lead to a significant increase in a speckle pattern contrast ratio, such that the projection apparatus may provide favorable image quality.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 26, 2022
    Assignees: Coretronic Corporation, Coretronics MEMS Corporation
    Inventors: Yi-Chien Lo, Shih-Hsiung Tseng
  • Patent number: 11287663
    Abstract: An optical transmitting module and a head mounted display device are provided. The optical transmitting module includes a waveguide and a first lens. The waveguide is located on a transmission path of an image beam. The waveguide includes a plurality of beam splitters configured to split the image beam the image beam into a first image beam and a second image beam. The second image beam reflected by the beam splitter is outputted from the waveguide, so as to display a virtual image. The first lens causes a plurality of virtual images displayed by a plurality of the second image beams reflected from different beam splitters at the same angle to coincide on a focal plane of the first lens. The head mounted display device can eliminate a ghost image phenomenon that occurs when the user observes the images displayed in a range closer to the eye.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 29, 2022
    Assignee: Coretronic Corporation
    Inventors: Yi-Chien Lo, Hung-Ta Chien, Hsin-Hsiang Lo
  • Publication number: 20220092014
    Abstract: During system power-on, Ethernet controllers in a server are initialized and configured by a Power-On-Reset (POR) mechanism. A user-defined time period can be selected to delay configuration of an Ethernet link to allow sufficient time for completion of the initialization of the Ethernet controller for post-boot operation. After configuration of an Ethernet PHY in the Ethernet controller is complete, an Ethernet link is established by exchanging messages with link partners according to the Ethernet protocol.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Inventor: Chia-yi CHIEN
  • Publication number: 20220043510
    Abstract: An eye-tracking system includes a light-transmitting display module, a reflecting mirror, an image system, and a processing unit. The light-transmitting display module includes a first side and a second side. The imaging system is disposed on the second side of the light-transmitting display module and includes a camera lens and an image sensor. The camera lens is coated with an optical film for receiving the light reflected by a user face. The image sensor is configured to provide an eye image based on the light reflected by the user face. The processing unit is configured to analyze the eye image so as to acquire the facial characteristics associated with the eyes of the user, wherein the user face is located on the first side of the light-transmitting display module when the user puts on the eye-tracking system.
    Type: Application
    Filed: February 17, 2021
    Publication date: February 10, 2022
    Inventors: LIANG FANG, Shao-Yi Chien
  • Publication number: 20220037356
    Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stack
    Type: Application
    Filed: October 14, 2021
    Publication date: February 3, 2022
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Chien
  • Publication number: 20220025532
    Abstract: A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Applicant: Sunrise Memory Corporation
    Inventors: Eli Harari, Wu-Yi Chien
  • Publication number: 20210397002
    Abstract: A holographic display device includes a display panel for emitting a first image light and a diffraction component on an optical path of the first image light. The first image light includes first and second colors of light. The diffraction component diffracts the first color light at a first diffraction efficiency and diffracts the second color light at a second diffraction efficiency. The first color light and the second color light after diffraction are mixed together in a second image light for generating holographic images. By emitting the first color light and the second color light in the first image light at the same grayscale value, a ratio of intensities of the first color light and the second color light becomes inversely proportional to a ratio of the first diffraction efficiency and the second diffraction efficiency.
    Type: Application
    Filed: September 15, 2020
    Publication date: December 23, 2021
    Inventors: TE-EN TSENG, TSAI-YI CHIEN
  • Publication number: 20210397927
    Abstract: A neural network system includes at least one memory and at least one processor. The memory is configured to store a front-end neural network, an encoding neural network, a decoding neural network and a back-end neural network. The processor is configured to execute the front-end neural network, the encoding neural network, the decoding neural network and the back-end neural network in the memory to perform operations including: utilizing the front-end neural network to output feature data; utilizing the encoding neural network to compress the feature data, and output compressed data which correspond to the feature data; utilizing the decoding neural network to decompress the compressed data, and output decompressed data which correspond to the feature data; and utilizing the back-end neural network to perform corresponding operations based on the decompressed data. A method of operating a neural network system is also disclosed herein.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 23, 2021
    Inventors: Yu-Ta CHEN, Feng-Ming LIANG, Shao-Yi CHIEN, Yu TSAO, Chen-En JIANG
  • Patent number: 11203645
    Abstract: The present disclosure relates to novel glycosynthase enzymes for glycoprotein engineering and/or homogeneous antibody remodeling. The enzyme variants, termed EndoSd-D232M and EndoSz-D234M, contain the glycan conjugation and/or modification activity at the conserved N297 glycosylation site of Fc region of an exemplary antibody. It has been demonstrated that the glycosynthase activities of EndoSd-D232M and EndoSz-D234M can be applied to various mAbs targeting different receptors, including, but not limited to, Globo H, SSEA-4, SSEA-3 series of receptors (OBI-888; Globo H ganglioside), Herceptin (Her 2 receptor), Perj eta (Her 2 receptor) and Vectibix (EGFR receptor). It has been found that both mAb-GlcNAc and mAb-GlucNAc(F) were suitable substrates for both EndoSd-D232M and EndoSz-D234M. The ADCC assay of related products, OBI-888-G2S2 and Herceptin-G2S2, showed that the remodeled homogeneous antibody, mAb-G2S2, has an increased relative activity ranging from 3 to 26 folds.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 21, 2021
    Assignee: OBI PHARMA, INC.
    Inventors: Cheng-Der Tony Yu, Yih Huang Hsieh, Yin-Cheng Hsieh, Teng-Yi Huang, Yi-Chien Tsai, Nan-Hsuan Wang, Pu-Ling Hu
  • Publication number: 20210390282
    Abstract: A training data increment method, an electronic apparatus and a computer-readable medium are provided. The training data increment method is adapted for the electronic apparatus and includes the following steps. A training data set is obtained, wherein the training data set includes a first image and a second image. An incremental image is generated based on the first image and the second image. A deep learning model is trained based on the incremental image.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 16, 2021
    Applicant: Wistron Corporation
    Inventors: Zhe-Yu Lin, Chih-Yi Chien, Kuan-I Chung
  • Patent number: 11194392
    Abstract: In a calibration process for an eye-tracking application, a calibration mark is displayed on an instrument, and the user is instructed to keep the gaze focused on the calibration mark. Next, a dynamic image is displayed on the instrument, and the user is instructed to move his head or the instrument as indicated by the dynamic image while keeping the gaze focused on the calibration mark. The ocular information of the user is recorded during the head movement or the instrument movement for calibrating the eye-tracking application.
    Type: Grant
    Filed: January 1, 2020
    Date of Patent: December 7, 2021
    Assignee: Ganzin Technology, Inc.
    Inventors: Kuan-Ling Liu, Liang Fang, Po-Jung Chiu, Yi-Heng Wu, Ming-Yi Tai, Yi-Hsiang Chen, Chia-Ming Chang, Shao-Yi Chien
  • Publication number: 20210364801
    Abstract: A holographic display device with reduced color shifting in relation to different colors includes a display panel and a diffraction component. The display panel emits a first color light having a first emission efficiency and a second color light having a second emission efficiency. The first emission efficiency is greater than the second emission efficiency. The diffraction component on an optical path of the first and second colors of light diffracts the first color light at a first diffraction efficiency and the second color light at a second diffraction efficiency to generate a holographic image, the first diffraction efficiency is less than the second diffraction efficiency.
    Type: Application
    Filed: September 30, 2020
    Publication date: November 25, 2021
    Inventors: TSAI-YI CHIEN, TE-EN TSENG
  • Patent number: 11180861
    Abstract: A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: November 23, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Wu-Yi Chien
  • Publication number: 20210358006
    Abstract: A system comprising a computer-readable storage medium storing at least one program, and a computer-implemented method for enhancing and personalizing an interactive marketplace. The systems and methods provided herein may allow a user to receive search results that are tailored to the user's personal preferences based on social and purchasing information known about the user. In addition, the systems and methods provided herein may provide shipping updates to a buyer that include a personalized message based on location information provided by the package being shipped. In addition, the systems and methods provided herein allow merchants to provide incentives and rewards for shoppers by participating in interactive shopping games.
    Type: Application
    Filed: July 27, 2021
    Publication date: November 18, 2021
    Inventors: Michael George Lenahan, Ben Lucas Mitchell, Chahn Chung, Myra Sandoval, Timothy Sean Suglian, Matthew Bret MacLaurin, James Ross Skorupski, Jesse Wolfe, Hsin-Yi Chien, Marie Jeanette Floyd Tahir, Jai Dandekar, Healey Cypher
  • Patent number: 11177281
    Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stack
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: November 16, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Chien
  • Patent number: 11176884
    Abstract: OLED pixel driving circuit, array substrate and display device are provided. The pixel driving circuit comprises a driving control unit, a first light emitting unit and a second light emitting unit. Two OLEDs share one driving control unit, so the two OLEDs alternately emit light. In this way, light emitting time of the OLEDs is reduced, number of parasitic capacitors and data lines in a panel is reduced, and aperture ratio of the OLED device is increased; and OLEDs are enabled to be in reverse bias in a non-light emitting display frame, so that OLEDs do not have to be in a DC bias state for a long time, and thus, aging of the OLED device is slowed down. No other reverse bias voltage is connected externally, difficulty of tracing of the pixel circuit and crosstalk from a bias voltage line to other signal lines are reduced.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: November 16, 2021
    Assignee: Shenzhen Chins Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Bobiao Chang, Xiaolong Chen, Yi-chien Wen
  • Publication number: 20210351088
    Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.
    Type: Application
    Filed: September 30, 2020
    Publication date: November 11, 2021
    Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee