Patents by Inventor Yi Chen

Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979156
    Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: May 7, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Chen Lu, Hsu-Chi Li, Yi-Jan Chen, Boy-Yiing Jaw, Chin-Tang Chuang, Chung-Hung Chen
  • Patent number: 11977756
    Abstract: A computer device, a setting method for a memory module, and a mainboard are provided. The computer device includes a memory module, a processor, and the mainboard. A basic input output system (BIOS) of the mainboard stores a custom extreme memory profile (XMP). When the processor executes the BIOS, so that the computer device displays a user interface (UI), the BIOS displays multiple default XMPs stored in the memory module and the custom XMP through the UI. The BIOS stores one of the default XMPs and the custom XMP to the memory module according to a selecting result of the one of the default XMPs and the custom XMP displayed on the UI.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: May 7, 2024
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Chia-Chih Chien, Sheng-Liang Kao, Chen-Shun Chen, Chieh-Fu Chung, Hua-Yi Wu
  • Patent number: 11979721
    Abstract: A wearable device can provide an audio module that is operable to provide audio output from a distance away from the ears of the user. For example, the wearable device can be worn on clothing of the user and direct audio waves to the ears of the user. Such audio waves can be focused by a parametric array of speakers that limit audibility by others. Thus, the privacy of the audio directed to the user can be maintained without requiring the user to wear audio headsets on, over, or in the ears of the user. The wearable device can further include microphones and/or connections to other devices that facilitate calibration of the audio module of the wearable device. The wearable device can further include user sensors that are configured to detect, measure, and/or track one or more properties of the user.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: May 7, 2024
    Assignee: Apple Inc.
    Inventors: Daniel A. Podhajny, Joshua A. Hoover, Nicholas R. Trincia, Yue Chen, Seul Bi Kim, Chad J. Miller, Kristen L. Cretella, Yi Zou, William Leith
  • Patent number: 11978640
    Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: May 7, 2024
    Inventors: Yi-Chen Lo, Yi-Shan Chen, Chih-Kai Yang, Pinyen Lin
  • Patent number: 11978267
    Abstract: A method and related system operations include obtaining a video stream with an image sensor of a camera device, detecting a plurality of target objects by executing a neural network model based on the video stream with a vision processor unit of the camera device. The method also includes generating a plurality of bounding boxes, determining a plurality of character sequences by, for each respective bounding box of the plurality of bounding boxes, performing a set of optical character recognition (OCR) operations to determine a respective character sequence of the plurality of character sequences. The method also includes updating a plurality of tracklets to indicate the plurality of bounding boxes and storing the plurality of tracklets in association with the plurality of character sequences in a memory of the camera device.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: May 7, 2024
    Assignee: Verkada Inc.
    Inventors: Mayank Gupta, Suraj Arun Vathsa, Song Cao, Yi Xu, Yuanyuan Chen, Yunchao Gong
  • Publication number: 20240142560
    Abstract: Within several applications the ability to localize an individual within an environment is beneficial. However, existing indoor localization approaches depend upon at least one of two assumptions. First, the subject(s) localization is achieved by localizing a wireless device carried by the subject and second, wireless fingerprints are established for the localization via a site survey being performed before a system can actually localize the subject(s). However, in many application scenarios, neither of the above two assumptions are true, namely that the user is not carrying an active wireless device or that the site has been surveyed. Accordingly, embodiments of the invention provide for subject localization by a dynamic calibration of wireless signals between a receiver and a transmitter, where neither the receiver or transmitter are associated with an electronic device carried or worn by the subject.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: YI GAO, MICHEL ALLEGUE MARTINEZ, XI CHEN, XUE LIU
  • Publication number: 20240142664
    Abstract: Two types of blue light blocking contact lenses are provided and are formed by curing different compositions. The first composition includes a blue light blocking component formed by mixing or reacting a first hydrophilic monomer and a yellow dye, a first colored dye component formed by mixing or reacting a second hydrophilic monomer and a first colored dye, at least one third hydrophilic monomer, a crosslinker, and an initiator. The first colored dye includes a green dye, a cyan dye, a blue dye, an orange dye, a red dye, a black dye, or combinations thereof. The second composition includes a blue light blocking component, at least one hydrophilic monomer, a crosslinker, and an initiator. The blue light blocking component is formed by mixing or reacting glycerol monomethacrylate and a yellow dye. Further, methods for preparing the above contact lenses are provided.
    Type: Application
    Filed: February 12, 2023
    Publication date: May 2, 2024
    Inventors: Han-Yi CHANG, Chun-Han CHEN, Tsung-Kao HSU, Wei-che WANG, Yu-Hung LIN, Wan-Ying GAO, Li-Hao LIU
  • Publication number: 20240143231
    Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Ning Chen, Jiangli Zhu, Yi-Min Lin, Fangfang Zhu
  • Publication number: 20240144467
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20240146316
    Abstract: A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL. The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.
    Type: Application
    Filed: October 19, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Shu Chen, Hsin-Chen Chen, Kuan Hung Lin, Jeng-Yi Lin
  • Publication number: 20240146205
    Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.
    Type: Application
    Filed: September 23, 2023
    Publication date: May 2, 2024
    Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
  • Publication number: 20240141716
    Abstract: The door sill includes a sill deck and a rail carrier assembly having a function of height adjustment. The rail carrier assembly is configured on the sill deck. The rail carrier assembly includes a rail cap, a rail carrier, an adjustment nut and an adjustment screw. The rail cap is snapped onto an upper end of the rail carrier. A groove is formed in the sill deck for the rail carrier to fit in. A nut installation hole is formed in the rail carrier. The adjustment nut is assembled at the nut installation hole, and is in threaded fit with the adjustment screw. The adjustment screw drives the adjustment nut to move up or down in an axial direction of the adjustment screw through rotation, thereby altering the height of the rail carrier fitted in the groove and altering the height of the rail cap.
    Type: Application
    Filed: December 26, 2022
    Publication date: May 2, 2024
    Inventors: Minghui CHEN, Yi CAO, James William Meeks, Xuhui WU
  • Publication number: 20240145421
    Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Neng CHEN, Zhong-Jie HONG, Chih-I CHO, Ming-Wei WENG, Chih-Han CHEN, Chiao-Yen WANG, Ying-Chan HUNG, Hong-Yi WU, CHENG-YEN HSIEH
  • Publication number: 20240147731
    Abstract: An interfacial layer is formed in a manner that enables a ferroelectric layer to be formed such that formation of ferroelectric crystalline phases (e.g., orthorhombic crystalline phases) in the ferroelectric layer is increased and formation of non-ferroelectric crystalline phases (e.g., monoclinic phases, tetragonal phases) in the ferroelectric layer is reduced. To achieve this, the grain size and/or other properties of the interfacial layer may be controlled during formation of the interfacial layer such that the grain size and/or other properties of the interfacial layer facilitate formation of a larger grain size in the ferroelectric layer. At larger grain sizes in the ferroelectric layer, the concentration of the ferroelectric crystalline phases in the crystal structure of the ferroelectric layer may be increased relative to if the ferroelectric layer were formed to a smaller grain size.
    Type: Application
    Filed: April 19, 2023
    Publication date: May 2, 2024
    Inventors: Yi-Hsuan CHEN, Kuen-Yi CHEN, Yi Ching ONG, Kuo-Ching HUANG
  • Publication number: 20240145246
    Abstract: Embodiments of the present technology include semiconductor processing methods. The methods may include providing a silicon-containing precursor and a dopant precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the semiconductor processing chamber. A silicon-containing material may be formed on the substrate. The methods may include contacting the silicon-containing material with the silicon-containing precursor and the dopant precursor. The methods may include forming a doped silicon-containing material on the silicon-containing material. The methods may include oxidizing the substrate. The oxidizing may form an oxidized doped silicon-containing material. The methods may include etching the oxidized doped silicon-containing material.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Yi Yang, In Soo Jung, Sean S. Kang, Srinivas D. Nemani, Papo Chen, Ellie Y. Yieh
  • Publication number: 20240146945
    Abstract: Provided is a method for video decoding including: receiving a control variable enabling adaptive switch between motion vector refinement (MVR) offset sets; receiving an indication variable enabling adaptive switch between codeword tables that binarize offset magnitudes in the MVR offset sets under the coding level; partitioning the video block into a first and a second geometric partition; selecting an MVR offset set based on the control variable; receiving syntax elements to determine a first and second MVR offsets applied to the first and second geometric partitions from the selected MVR offset set; obtaining a first and second MVs from a candidate list for the first and the second geometric partition; calculating a first and second refined MVs based on the first and second MVs and the first and second MVR offsets; and obtaining prediction samples based on the first and second refined MVs.
    Type: Application
    Filed: December 14, 2023
    Publication date: May 2, 2024
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Xiaoyu XIU, Wei CHEN, Che-Wei KUO, Hong-Jheng ZHU, Ning YAN, Yi-wen CHEN, Xianglin WANG, Bing YU
  • Publication number: 20240145650
    Abstract: A package comprises a substrate including a first surface, and an upper conductive layer arranged on the first surface, a first light-emitting unit arranged on the upper conductive layer, and comprises a first semiconductor layer, a first substrate, a first light-emitting surface and a first side wall, a second light-emitting unit, which is arranged on the upper conductive layer, and comprises a second light-emitting surface and a second side wall, a light-transmitting layer arranged on the first surface and covers the upper conductive layer, the first light-emitting unit, and the second light-emitting unit, a light-absorbing layer, which is arranged between the substrate and the light-transmitting layer in a continuous configuration of separating the first light-emitting unit and the second light-emitting unit from each other, and a reflective wall arranged on the first side wall, wherein a height of the reflective wall is lower than that of the light-absorbing layer.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Inventors: Shau-Yi CHEN, Tzu-Yuan LIN, Wei-Chiang HU, Pei-Hsuan LAN, Min-Hsun HSIEH
  • Publication number: 20240142237
    Abstract: A localization device and a localization method for a vehicle are provided. The localization device includes an inertia measurer, an encoder, an image capturing device, and a processor. The processor obtains an encoded data by the encoder to generate a first odometer data, obtains an inertial data by the inertia measurer to generate a heading angle estimation data, and obtains an environmental image data by the image capturing device to generate a second odometer data. In a first fusion stage, the processor fuses the heading angle estimation data and the first odometer data to generate first fusion data. In a second fusion stage, the processor fuses the first fusion data, the heading angle estimation data and the second odometer data to generate pose estimation data corresponding to the localization device.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Jhong Chen, Pei-Jung Liang, Ren-Yi Huang
  • Publication number: 20240145520
    Abstract: The present disclosure provides a method for fabricating an image sensor. The method includes the following operations. A cavity is formed at a first surface of a substrate. A germanium layer is formed in the cavity. A first heavily doped region is formed in the germanium layer by an implantation operation. A second heavily doped region is formed at a position proximal to a top surface of the germanium layer, wherein the second heavily doped region is laterally surrounded by the first heavily doped region from a top view perspective. An interconnect structure is formed over the germanium layer.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: JHY-JYI SZE, SIN-YI JIANG, YI-SHIN CHU, YIN-KAI LIAO, HSIANG-LIN CHEN, KUAN-CHIEH HUANG, JUNG-I LIN
  • Patent number: D1025930
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: May 7, 2024
    Assignee: EMOMO TECHNOLOGY CO., LTD.
    Inventors: Wei Zhou, Wenji Tang, Jing Song, Yushu Zhao, Xiaolian Zhou, Zhigang Wang, Jun Yang, Qishuang Lu, Juntao Chen, Yi Wang