Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

Abstract: Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract: Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.

Abstract: Implementations of the present disclosure generally relate to improved semiconductor devices and methods of manufacture thereof. More specifically, implementations disclosed herein relate to a semiconductor device having an improved contact interface between the semiconductor material and metal material and methods of manufacture thereof. The method includes forming a semiconductor layer on a silicon substrate, forming an interfacial layer over the semiconductor layer, and forming a metal contact layer over the interfacial layer. The interfacial layer comprises one or more of germanium, boron, gallium, indium, thallium, arsenic, antimony, tin, silicon, and phosphorus, and has a thickness of between about 50 angstroms and about 100 angstroms. The interfacial layer improves the quality of the contact interface between the semiconductor material and metal material.

Abstract: Embodiments of the present disclosure generally relate to methods for trench filling of high quality epitaxial silicon-containing material without losing selectivity of growth to dielectrics such as silicon oxides and silicon nitrides. The methods include epitaxially growing a silicon-containing material within a trench formed in a dielectric layer by exposing the trench to a gas mixture comprising a halogenated silicon compound and a halogenated germanium compound. In one embodiment, the halogenated silicon compound includes chlorinated silane and halogenated germanium compound includes chlorinated germane.

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

Abstract: Methods for forming transistors are provided. A substrate is placed in a processing chamber, and a plurality of epitaxial features is formed on the substrate. The epitaxial feature has at least a surface having the (110) plane and a surface having the (100) plane. An etchant or a gas mixture including an etchant and an etch enhancer or an etch suppressor is introduced into the processing chamber to remove a portion of the epitaxial feature. Etch selectivity between the surface having the (110) plane and the surface having the (100) plane can be tuned by varying the pressure within the processing chamber, the ratio of the flow rate of the etchant or gas mixture to the flow rate of a carrier gas, and/or the ratio of the flow rate of the etch enhancer or suppressor to the flow rate of the etchant.

Abstract: Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.

Abstract: The present disclosure provides methods for forming nanowire spacers for nanowire structures with desired materials in horizontal gate-all-around (hGAA) structures for semiconductor chips. In one example, a method of forming nanowire spaces for nanowire structures on a substrate includes performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer, filling the recess with a dielectric material, and removing the dielectric layer over filled from the recess.

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract: Embodiments of the present disclosure generally relate to methods for trench filling of high quality epitaxial silicon-containing material without losing selectivity of growth to dielectrics such as silicon oxides and silicon nitrides. The methods include epitaxially growing a silicon-containing material within a trench formed in a dielectric layer by exposing the trench to a gas mixture comprising a halogenated silicon compound and a halogenated germanium compound. In one embodiment, the halogenated silicon compound includes chlorinated silane and halogenated germanium compound includes chlorinated germane.

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract: Methods for depositing a group III-V layer on a substrate are disclosed herein. In some embodiments a method includes depositing a first layer comprising at least one of a first Group III element or a first Group V element on a silicon-containing surface oriented in a <111> direction at a first temperature ranging from about 300 to about 400 degrees Celsius; and depositing a second layer comprising second Group III element and a second Group V element atop the first layer at a second temperature ranging from about 300 to about 600 degrees Celsius.

Abstract: Embodiments described herein generally relate to an apparatus for depositing materials on a substrate. The apparatus includes a substrate support assembly. The substrate support assembly includes a susceptor and a substrate support ring disposed on the susceptor. The substrate support ring has a first surface for receiving the substrate and a second surface opposite the first surface. The second surface includes at least three protrusions and each protrusion has a tip that is in contact with the susceptor. The substrate support ring is comprised of a material having poor thermal conductivity, and the contact area between the substrate support ring and the susceptor is minimized, resulting in minimum unwanted heat conduction from the susceptor to the edge of the substrate.

Abstract: In one embodiment, a susceptor for a thermal processing chamber is provided. The susceptor includes a base having a front side and a back side made of a thermally conductive material opposite the front side, wherein the base includes a peripheral region surrounding a recessed area having a thickness that is less than a thickness of the peripheral region, and a plurality of raised features protruding from one or both of the front side and the back side.

Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.

Abstract: Methods for chemical mechanical planarization of patterned wafers are provided herein. In some embodiments, methods of processing a substrate having a first surface and a plurality of recesses disposed within the first surface may include: depositing a first material into the plurality of recesses to predominantly fill the plurality of recesses with the first material; depositing a second material different from the first material into the plurality of recesses and atop the substrate to fill the plurality of recesses and to form a layer atop the first surface; and planarizing the second material using a first slurry in a chemical mechanical polishing tool until the first surface is reached. In some embodiments, a second slurry, different than the first slurry, is used to planarize the substrate to a first level.