Patents by Inventor Yi-Chun Chen

Yi-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384269
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20220367664
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 17, 2022
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Patent number: 11502076
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 11437484
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Publication number: 20220203449
    Abstract: A metal member includes a base and a mesh structure arranged on the base. The mesh structure includes a plurality of three-dimensional unit cell structures coupled together in an orderly manner. Each unit cell structure includes at least one first node. The plurality of unit cell structures is coupled together by the at least one first node.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 30, 2022
    Inventors: CHEN-YU HONG, YI-CHUN CHEN, ZHENG-GANG YANG
  • Publication number: 20220181217
    Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Inventors: Yi-Chun Chen, Ryan Chia-Jen Chen, Shu-Yuan Ku, Ya-Yi Tsai, I-Wei Yang
  • Patent number: 11347363
    Abstract: A touch electrode structure and a capacitive touch system are provided. The touch electrode structure includes: a substrate; a plurality of first electrode series each including a plurality of first electrodes; a plurality of second electrode series each including a plurality of second electrodes; and at least one connecting wire. Each of the second electrode series includes at least one electrode group, and the at least one electrode group includes two of the second electrodes. The two of the second electrodes are electrically connected to each other on a first surface of the substrate, and at least one of the two of the second electrodes is electrically connected to one of the second electrodes adjacent to the at least one of the two of the second electrodes.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 31, 2022
    Assignee: SILICON INTEGRATED SYSTEMS CORP.
    Inventors: Wei-En Shih, Ying-Jyh Yeh, Yi-Chun Chen
  • Publication number: 20220156910
    Abstract: A method for generating reconstruction a reconstructed image is adapted to an input image having a target object. The method comprises converting the input image into a feature map with vectors by an encoder; performing a training procedure according to training images of reference objects to generate feature prototypes associated with the training images and store the feature prototypes to a memory; selecting a part of feature prototypes from the feature prototypes stored in the memory according to similarities between the feature prototypes and the feature vectors; generating a similar feature map according the part of feature prototypes and weights, wherein the weights represents similarities between the part of feature prototypes and the feature vectors; and converting the similar feature map into the reconstructed image by a decoder; wherein the encoder, the decoder and the memory form an auto-encoder.
    Type: Application
    Filed: February 9, 2021
    Publication date: May 19, 2022
    Inventors: Daniel Stanley Young Tan, Yi-Chun Chen, Trista Pei-Chun Chen, Wei-Chao Chen
  • Patent number: 11319434
    Abstract: A block copolymer is provided. The block copolymer includes a first block including repeat units represented by formula (I), and a second block connected to the first block and including repeat units represented by formula (II) or (III). The disclosure also provides a method for preparing the block copolymer and a thin film structure including the same.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: May 3, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Meei-Yu Hsu, Yi-Chun Chen, Kai-Chi Chen
  • Patent number: 11315229
    Abstract: A method for training a defect detector comprises: obtaining a first reference image of a first reference object, wherein the first reference object has a defect and the first reference image has a first label indicating the defect; training a reconstruction model according to a second reference image of a second reference object associated with the first reference object, wherein a defect level of the second reference object is in a tolerable range with an upper limit; obtaining a target image of a target object associated with the first reference object and the second reference object; generating a second label according to the target image, the reconstruction model and an error calculation procedure, wherein the second label comprises a defect of the target object; and training a defect detector by performing a machine learning algorithm according to the first reference image, the target image and the second label.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: April 26, 2022
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Yi-Chun Chen, Trista Pei-Chun Chen, Daniel Stanley Young Tan, Wei-Chao Chen
  • Publication number: 20220093584
    Abstract: A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.
    Type: Application
    Filed: October 21, 2020
    Publication date: March 24, 2022
    Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Chien-Liang Wu, Te-Wei Yeh, Yi-Chun Chen
  • Patent number: 11273410
    Abstract: An extracted material for forward osmosis is provided. The extracted material includes a first ionic compound, a second ionic compound and a third ionic compound, which are represented by formula {K[A+(R1)(R2)(R3)]p}(X?)c(Y?)d. X? is the same as Y? in the first ionic compound. X? is the same as Y? in the second ionic compound. X? in the first ionic compound is different from X? in the second ionic compound. X? differs from Y? in the third ionic compound. X? in the third ionic compound is the same as X? in the first ionic compound or X? in the second ionic compound. Y? in the third ionic compound is the same as Y? in the first ionic compound or Y? in the second ionic compound. A method for preparing an extracted material and a forward-osmosis water desalination system using the same are also provided.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: March 15, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Chun Chen, Po-I Liu, Chia-Hua Ho, Yeu-Ding Chen, David Chiuni Wang, Ren-Yang Horng, Kai-Chi Chen
  • Patent number: 11264287
    Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chun Chen, Ryan Chia-Jen Chen, Shu-Yuan Ku, Ya-Yi Tsai, I-Wei Yang
  • Publication number: 20220035433
    Abstract: Systems, apparatuses, and methods for saving power on a bus interface are described. A system includes a host, a device, and a repeater interposed between the host and the device. While the host and device are in a low-power state, the repeater monitors a first bus to determine if the device has woken up. When the repeater detects a remote wake-up event initiated by the device, the repeater generates an interrupt which is sent to the host. The host responds to the interrupt by initiating a resume wake-up event procedure that assumes the device is still asleep. In this way, the host is able to stay in the low-power state longer while also using a wake-up procedure that does not require the host to be aware of the existence of the repeater.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Inventors: Itay Franko, Derek Iwamoto, Mark Ferdinand Damarillo, William O. Ferry, Yi-Chun Chen
  • Patent number: 11235283
    Abstract: An ionic liquid and a forward osmosis process employing the same are provided. The ionic liquid has a structure represented by Formula (I) ABn??Formula (I), wherein A is n is 1 or 2; m is 0, or an integer from 1 to 7; R1 and R2 are independently methyl or ethyl; k is an integer from 3 to 8; B is i is independently 1, 2, or 3; and j is 5, 6, or 7. The forward osmosis process employing the ionic liquid is used to desalinate a brine via a forward osmosis (FO) model.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: February 1, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-I Liu, Hsin Shao, Min-Chao Chang, Yi-Chun Chen, Chiung-Hui Huang, Chia-Hua Ho, David Chiuni Wang, Ren-Yang Horng
  • Patent number: 11201856
    Abstract: A method, computer system, and a computer program product for securing message transmission is provided. The present invention may include linking, by a first terminal device, a communication interface to a first communication channel for a target application. The present invention may include, in response to a first message being inputted in the communication interface, encrypting, by the first terminal device, the first message with a key for the first communication channel. The present invention may include, transmitting, by the first terminal device, the encrypted first message via the first communication channel.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Wen-Ping Chi, Chao Yuan Huang, Yi-Chun Chen, Ting-Yi Wang
  • Publication number: 20210383168
    Abstract: A method for labeling image comprises: obtaining a target image of a target object; generating a reconstruction image according to the target image and a reconstruction model, wherein the reconstruction model is trained with a plurality of reference images and a machine learning algorithm, each of the reference images is an image of a reference object whose defect level is in a tolerable range with an upper limit, and each of the reference objects is associated with the target object; generating a first difference image and a second difference image respectively by performing a first difference algorithm and a second difference algorithm respectively according to the target image and the reconstruction image; and generating an output image by performing a pixel-scale operation according to the first difference image and the second difference image, wherein the output image includes a label indicating a defect of the target object.
    Type: Application
    Filed: June 18, 2020
    Publication date: December 9, 2021
    Inventors: YI-CHUN CHEN, Trista Pei-Chun Chen, Daniel Stanley Young Tan, Wei-Chao Chen
  • Publication number: 20210383526
    Abstract: A method for training a defect detector comprises: obtaining a first reference image of a first reference object, wherein the first reference object has a defect and the first reference image has a first label indicating the defect; training a reconstruction model according to a second reference image of a second reference object associated with the first reference object, wherein a defect level of the second reference object is in a tolerable range with an upper limit; obtaining a target image of a target object associated with the first reference object and the second reference object; generating a second label according to the target image, the reconstruction model and an error calculation procedure, wherein the second label comprises a defect of the target object; and training a defect detector by performing a machine learning algorithm according to the first reference image, the target image and the second label.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 9, 2021
    Inventors: YI-CHUN CHEN, Trista Pei-Chun CHEN, Daniel Stanley Young Tan, Wei-Chao CHEN
  • Patent number: 11176419
    Abstract: A method for labeling image comprises: obtaining a target image of a target object; generating a reconstruction image according to the target image and a reconstruction model, wherein the reconstruction model is trained with a plurality of reference images and a machine learning algorithm, each of the reference images is an image of a reference object whose defect level is in a tolerable range with an upper limit, and each of the reference objects is associated with the target object; generating a first difference image and a second difference image respectively by performing a first difference algorithm and a second difference algorithm respectively according to the target image and the reconstruction image; and generating an output image by performing a pixel-scale operation according to the first difference image and the second difference image, wherein the output image includes a label indicating a defect of the target object.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: November 16, 2021
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Yi-Chun Chen, Trista Pei-Chun Chen, Daniel Stanley Young Tan, Wei-Chao Chen
  • Patent number: D947138
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: March 29, 2022
    Assignee: TIMOTION TECHNOLOGY CO., LTD.
    Inventor: Yi-Chun Chen