Abstract: Apparatuses and methods for decoding short physical uplink control channel for. In one embodiment, a method implemented in a network node includes determining whether to use one of a coherent detection and a non-coherent detection of a physical uplink control channel, PUCCH, based at least in part on information relating to the wireless device; configuring the wireless device with a first sequence and a second sequence for a hybrid automatic repeat request, HARQ, acknowledgement information on the PUCCH based at least in part on the determination of the one of the coherent detection and the non-coherent detection, the first sequence corresponding to a HARQ acknowledgement, HARQ-ACK, and the second sequence corresponding to a HARQ non-acknowledgement, HARQ-NACK; and receiving the HARQ acknowledgement information on the PUCCH according to the first sequence and the second sequence.

Abstract: A method to treat hepatoma with dengue viruses which infect liver tumor stem cells for annihilation of hepatocellular carcinoma tissues. The liver tumor stem cells expressing the biomarker of CD133 in a tumor part are the objects infected by dengue viruses preferentially and killed due to specific protein expressions for suppression of hepatoma.

Abstract: In some embodiments, a method performed by a wireless device comprises: obtaining a timing advance (TA) value for uplink transmissions; receiving a grant for a radio resource control (RRC) inactive mode uplink transmission; measuring a reference signal associated with each beam of a plurality of beams at a first time; selecting a first beam based on the measured reference signals; measuring a reference signal associated with each beam of a plurality of beams at a second time in preparation for the RRC inactive mode uplink transmission; selecting a second beam for which the measuring was performed at the second time; and when the first selected beam is the same as the second selected beam and the reference signal for the first selected beam is within a threshold value of the reference signal for the second selected beam, transmitting the RRC inactive mode uplink transmission using the obtained TA.

Abstract: A probe apparatus and a wafer inspection method are provided. The probe apparatus includes a chuck configured to support a wafer, a track surrounding the chuck, a tester disposed on the track and having a probe, and a processing unit in communication with the tester and configured to move the tester circumferentially around the wafer such that the probe is moved from a first portion on the wafer to a second portion on the wafer.

Abstract: A semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device includes a source via electrically coupled to the source feature and a drain via electrically coupled to the drain feature. The semiconductor device includes a source via metal line disposed over and directly connected to the source via. The semiconductor device includes and a drain via metal line disposed over and directly connected to the drain via. The source via metal line has two first outer edges extending lengthwise along a first direction and at least one of the first outer edges is substantially aligned with an edge of the source via from a top view. The drain via metal line has two second outer edges extending lengthwise along the first direction and the two second outer edges are offset from edges of the drain via from a top view.

Abstract: The present disclosure provides a method of operating a benchmark device embedded on a semiconductor wafer. The method includes applying a first voltage to a first electrode of the benchmark device, and applying a second voltage to a second electrode of the benchmark device. The method further includes electrically isolating a first component of the benchmark device from a second component of the benchmark device through a disconnecting switch connected between the first component and the second component.

Abstract: A semiconductor wafer, a benchmark device embedded on a semiconductor wafer, and a method of operating a benchmark device embedded on a semiconductor wafer are provided. The semiconductor wafer includes a benchmark device disposed within a scribe line of the semiconductor wafer. The benchmark device includes a transistor, a diode, and a disconnecting switch electrically connected to the transistor and the diode. The disconnecting switch is configured to form a conductive path between the transistor and the diode at a first stage, and to electrically isolate the transistor from the diode at a second stage.

Abstract: Embodiments include methods for a wireless device configured for random access to a cell of a wireless network. Such methods include transmitting, to a network node during a random-access procedure in the cell, a first indication of at least one capability of the wireless device. Such methods also include communicating with the network node, in one or more subsequent messages of the random-access procedure, using a configuration corresponding to the at least one capability indicated by the first indication. Other embodiments include complementary methods for a network node configured to support random access by wireless devices, as well as wireless devices and network nodes configured to perform such methods.

Abstract: A light-emitting element is provided, including a semiconductor structure, a reflective structure, first insulating structures, a conductive structure, and first and second pads. The reflective structure is disposed on the semiconductor structure. The first insulating structure includes first and second insulating portions covering first and second portions respectively, and a gap exposes a third portion between the first and second portions. The conductive structure includes first and second conductive portion. The first conductive portion is disposed on the first insulating portion to contact the semiconductor structure. The second conductive portion is disposed on the second insulating portion to contact the third portion through the gap. The first and second pads are respectively disposed on the first and second conductive portions. Each of the structures below the first and second pads are in flat-type bonding to enhance stress resistance.

Abstract: A method by a reduced capability wireless device includes receiving system information from a network node. The system information comprising information specific to the reduced capability wireless device. The reduced capability wireless device performs an operation using at least the information specific to the reduced capability wireless device received in the system information.

Abstract: A method of operating a wireless device in a wireless communication network. The method includes detecting first synchronization signaling of a first cell on first time and frequency resources. The first synchronization signaling comprises at least a first synchronization signal and a second synchronization signal. The method further includes detecting indication signaling on second time and frequency resources. The second time and frequency resources are derived based on the first time and frequency resources. The method further includes accessing the first cell if the indication signaling is detected on the second time and frequency resources. Accessing the first cell includes decoding a first system information message on a broadcast channel of the first cell. The first system information message indicates time and frequency resources of a first resource set. The disclosure also pertains to related devices and methods.

Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.

Abstract: A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.

Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.

Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.

Abstract: An upper gastrointestinal bleeding monitoring system includes a detection device and a signal processing device to determine bleeding condition of an upper gastrointestinal tract by using relation of time and intensity ratios of RGB three primary colors. The detecting device is placed to the upper gastrointestinal tract of a patient via his/her mouth or nasal passage and then stay the upper gastrointestinal tract for several days for detection of bleeding. The signal processing device may receive and display signal from the detection device to help medical professionals check if bleeding occurs in an upper gastrointestinal tract. Moreover, a procedure of determination of bleeding in an upper gastrointestinal tract with the upper gastrointestinal bleeding monitoring system is described.

Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.

Abstract: A light-emitting element is provided, including a semiconductor structure, a reflective structure, first and second insulating structures, a conductive structure, and first and second pads. The reflective structure is disposed on the semiconductor structure. The first insulating structure includes first and second protrusions covering first and second portions respectively, and a first recession exposes a third portion between the first and second portions. The conductive structure includes first and second conductive portion. The first conductive portion is disposed on the first protrusion to contact the semiconductor structure. The second conductive portion is disposed on the second protrusion to contact the third portion through the first recession. The first and second pads are respectively disposed on the first and second conductive portions. Each of the structures below the first and second pads are in flat-type bonding to enhance stress resistance.

Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A gate dielectric layer covers opposite sidewalls and a bottom of the conductive gate stack. A first gate spacer layer and a second gate spacer layer respectively cover portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack. A source/drain contact structure is separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer. A first insulating capping feature covers the conductive gate stack and is separated from the second gate spacer layer by the gate dielectric layer, and a second insulating capping feature covers the source/drain contact structure. An upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.