Patents by Inventor Yi Lin

Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145600
    Abstract: A semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the source electrode and the drain electrode are arranged on one side of the gate insulating layer, wherein the gate insulating layer includes multilayer oxide films stacked on each other and at least one interface layer between the multilayer oxide films, and the material of the at least one interface layer is different from the material of the oxide films.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih WEN, Yi-Lin YANG, Hai-Ching CHEN
  • Publication number: 20240146205
    Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.
    Type: Application
    Filed: September 23, 2023
    Publication date: May 2, 2024
    Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
  • Publication number: 20240147812
    Abstract: The present application provides an organic light emitting diode (OLED) display panel and a method of manufacturing the same, and a display terminal. The OLED display panel includes an array substrate, a protective layer and a cathode. The array substrate includes a first auxiliary electrode, a second auxiliary electrode, and a third auxiliary electrode. The third auxiliary electrode is connected to the first auxiliary electrode and the second auxiliary electrode. The protective layer is provided with an undercut opening exposing a portion of the third auxiliary electrode. The cathode extends into the undercut opening and is connected to the third auxiliary electrode.
    Type: Application
    Filed: September 26, 2023
    Publication date: May 2, 2024
    Inventors: Huan DUAN, Yi ZHUO, Fangmei LIU, Zhiwei SONG, Gaobo LIN, Kai HU
  • Publication number: 20240142664
    Abstract: Two types of blue light blocking contact lenses are provided and are formed by curing different compositions. The first composition includes a blue light blocking component formed by mixing or reacting a first hydrophilic monomer and a yellow dye, a first colored dye component formed by mixing or reacting a second hydrophilic monomer and a first colored dye, at least one third hydrophilic monomer, a crosslinker, and an initiator. The first colored dye includes a green dye, a cyan dye, a blue dye, an orange dye, a red dye, a black dye, or combinations thereof. The second composition includes a blue light blocking component, at least one hydrophilic monomer, a crosslinker, and an initiator. The blue light blocking component is formed by mixing or reacting glycerol monomethacrylate and a yellow dye. Further, methods for preparing the above contact lenses are provided.
    Type: Application
    Filed: February 12, 2023
    Publication date: May 2, 2024
    Inventors: Han-Yi CHANG, Chun-Han CHEN, Tsung-Kao HSU, Wei-che WANG, Yu-Hung LIN, Wan-Ying GAO, Li-Hao LIU
  • Publication number: 20240145372
    Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Wen TSAO, Wen-Chen HSIEH, Yi-Lin TSAI, Hsiu-Fang CHIEN
  • Publication number: 20240139199
    Abstract: The present disclosure provides a use of a pharmaceutical composition including adenine and/or a pharmaceutically acceptable salt thereof in a manufacture of a medicament for treating diabetic ulcers, and the medicament can effectively accelerate and enhance wound healing of diabetic ulcers and prevent scar formation.
    Type: Application
    Filed: March 25, 2022
    Publication date: May 2, 2024
    Inventors: Jen-Yi Chio, Han-Min Chen, Jiun-Tsai Lin, Yi-Fang Cheng, Guang-Huar Young, Chun-Fang Huang
  • Publication number: 20240139337
    Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Cheng-Hsun WU, SI-HAN WU, YI-PING CHEN, RONG-LIN ZHANG, CHUNG-YUAN MOU, Yu-Tse LEE
  • Publication number: 20240145650
    Abstract: A package comprises a substrate including a first surface, and an upper conductive layer arranged on the first surface, a first light-emitting unit arranged on the upper conductive layer, and comprises a first semiconductor layer, a first substrate, a first light-emitting surface and a first side wall, a second light-emitting unit, which is arranged on the upper conductive layer, and comprises a second light-emitting surface and a second side wall, a light-transmitting layer arranged on the first surface and covers the upper conductive layer, the first light-emitting unit, and the second light-emitting unit, a light-absorbing layer, which is arranged between the substrate and the light-transmitting layer in a continuous configuration of separating the first light-emitting unit and the second light-emitting unit from each other, and a reflective wall arranged on the first side wall, wherein a height of the reflective wall is lower than that of the light-absorbing layer.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Inventors: Shau-Yi CHEN, Tzu-Yuan LIN, Wei-Chiang HU, Pei-Hsuan LAN, Min-Hsun HSIEH
  • Publication number: 20240146316
    Abstract: A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL. The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.
    Type: Application
    Filed: October 19, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Shu Chen, Hsin-Chen Chen, Kuan Hung Lin, Jeng-Yi Lin
  • Patent number: 11974367
    Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: April 30, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Ming-Chieh Cheng, Po-Yen Chen, Shih-Chieh Chang, Kuan-Hsien Tu, Xiu-Yi Lin, Ling-Chun Wang
  • Patent number: 11973958
    Abstract: Methods and apparatus of video coding using sub-block based affine mode are disclosed. According to this method, control-point motion vectors (MVs) associated with the affine mode are determined for a block. A sub-block MV is derived for a target sub-block of the block from the control-point MVs for the block. A prediction offset is determined for a target pixel of the target sub-block using information comprising a pixel MV offset from the sub-block MV for the target pixel according to Prediction Refinement with Optical Flow (PROF). The target pixel of the target sub-block is encoded or decoded using a modified predictor. The modified prediction is generated by clipping the prediction offset to a target range and combining the clipped prediction offset with an original predictor.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 30, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Tzu-Der Chuang, Ching-Yeh Chen, Zhi-Yi Lin
  • Patent number: 11972139
    Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: April 30, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Chun-Wei Tsao, Hsiao-Yi Lin, Wei Lin
  • Patent number: 11973261
    Abstract: An antenna structure with wide radiation bandwidth in a reduced physical space includes a metallic housing, a first feed portion, and a second feed portion. The metallic housing includes a metallic side frame and a metallic back board. The metallic side frame defines a slot, and first and second gaps. The metallic side frame between the first gap and one end of the slot forms a first radiation portion. The second gap divides the first radiation portion into first and second radiation sections. The first feed portion feeds current and signal to the first radiation section, and the first radiation section works in a GPS mode and a WIFI 2.4 GHz mode. The second feed portion feeds current and signal to the second radiation section, and the second radiation section works in a WIFI 5 GHz mode.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 30, 2024
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Kun-Lin Sung, Yung-Chin Chen, Yi-Chieh Lee
  • Patent number: 11969288
    Abstract: A three-dimensional ultrasonic imaging method includes transmitting an ultrasonic wave to a fetal head; receiving an ultrasonic echo, obtaining an ultrasonic echo signal, and obtaining the three-dimensional volume data of the fetal head according to the ultrasonic echo signal; according to the characteristics of a median sagittal section of the fetal head, detecting the median sagittal section in the three-dimensional volume data; and displaying the median sagittal section.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 30, 2024
    Assignee: Shenzhen Mindray Bio-Medical Electronics Co., Ltd.
    Inventors: Yaoxian Zou, Muqing Lin, Zhijie Chen, Yi Xiong, Bin Yao
  • Patent number: 11972951
    Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
  • Publication number: 20240135485
    Abstract: The disclosure relates to tuning configuration parameters for graphics pipeline for better user experience. A device for graphics processing, comprising: hardware engines; a graphics pipeline at least partly implemented by the hardware engines; and a tuner, coupled to the hardware engines and the graphics pipeline, the tuner to: collect statuses of the device during runtime for a previous frame; determine configuration parameters based on the collected statuses, the configuration parameters associated with three-dimensional 3D rendering, pre-processing and video encoding of the graphics pipeline; and tune the graphics pipeline with the determined configuration parameters for processing a next frame.
    Type: Application
    Filed: September 1, 2023
    Publication date: April 25, 2024
    Applicant: Intel Corporation
    Inventors: Fan He, Yi Qian, Ning Luo, Yunbiao Lin, Changliang Wang, Ximin Zhang
  • Publication number: 20240136227
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Publication number: 20240131538
    Abstract: An annular airflow regulating apparatus includes a cup-shaped element and an adjustment element. The cup-shaped element has a bowl and a bottom, integrated to form a first chamber. The bottom has a tapered channel parallel to an axis and penetrating through the bottom. A ring-shaped groove is disposed between the tapered channel and the bottom. The ring-shaped groove has an annular plane perpendicular to the axis. The adjustment element, having a tapered portion and second holes, is movably disposed in the cup-shaped element. The tapered portion protrudes into the tapered channel A tapered annular gap is formed between the tapered portion and the tapered channel. When the adjustment element is moved with respect to the cup-shaped element, a width of the tapered annular gap is varied, and thereupon a flow rate and velocity of the process gas would be varied accordingly.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 25, 2024
    Inventors: CHEN-CHUNG DU, Ming-Jyh Chang, Chang-Yi Chen, Ming-Hau Tsai, Ko-Chieh chao, Yi-Wei Lin
  • Publication number: 20240133949
    Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Lin Yang, Chin-Wei Lin, Po-Chao Tsao, Tung-Hsing Lee, Chia-Jung Ni, Chi-Ming Lee, Yi-Ju Ting
  • Patent number: 11966587
    Abstract: A method for optimizing a Polar-RNNA quantizer of MLC NAND flash based on deep learning comprises the following steps: Step S1: transforming an MLC flash detection task into a deep learning task, and obtaining three hard-decision read thresholds based on a neural network; Step S2: expanding six soft-decision read thresholds based on the three hard-decision read thresholds; Step S3: constructing an LLR mapping table, and obtaining new LLR information of MLC flash based on the LLR mapping table; Step S4: symmetrizing an MLC flash channel, and performing density evolution; and Step S5: optimizing the soft-decision read thresholds based on a genetic algorithm to obtain an optimal quantization interval. According to the invention, polar codes can be directly used for MLC flash channels without the arduous work of MLC flash channel modeling, so that the reliability of MLC flash is effectively improved.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 23, 2024
    Assignee: FUZHOU UNIVERSITY
    Inventors: Pingping Chen, Zhen Mei, Yi Fang, Xu Luo, Zhijian Lin, Feng Chen, Riqing Chen