Patents by Inventor Yi Lin

Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961892
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 11962328
    Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: April 16, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
  • Patent number: 11961998
    Abstract: Provided is a method of producing multiple particulates, the method comprising: (a) dispersing multiple primary particles of an anode active material, having a particle size from 2 nm to 20 ?m, and particles of a polymer foam material, having a particle size from 50 nm to 20 ?m, and an optional adhesive or binder in a liquid medium to form a slurry; and (b) shaping the slurry and removing the liquid medium to form the multiple particulates having a diameter from 100 nm to 50 ?m; wherein at least one of the multiple particulates comprises a polymer foam material having pores and a single or a plurality of the primary particles embedded in or in contact with the polymer foam material, wherein the primary particles have a total solid volume Va, and the pores have a total pore volume Vp, and the volume ratio Vp/Va is from 0.1/1.0 to 10/1.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: April 16, 2024
    Assignee: Honeycomb Battery Company
    Inventors: Yi-Jun Lin, Yen-Po Lin, Sheng-Yi Lu, Bor Z. Jang
  • Patent number: 11961770
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Publication number: 20240120845
    Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. The second driving signal includes a resonant pulse having a resonant pulse width and a ZVS pulse during the DCM operation. The resonant pulse is configured to demagnetize the transformer. The resonant pulse has a first minimum resonant period for a first level of the output load and a second minimum resonant period for a second level of the output load. The first level is higher than the second level and the second minimum resonant period is shorter than the first minimum resonant period.
    Type: Application
    Filed: April 14, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
  • Publication number: 20240120846
    Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.
    Type: Application
    Filed: April 14, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
  • Publication number: 20240119023
    Abstract: A method for communication within a multicore system which includes a primary programmable logic device (PLD) and a secondary PLD installed respectively on a primary motherboard and a secondary motherboard includes steps of: A) by the primary PLD, determining whether the primary motherboard is connected to the secondary motherboard; B) by the primary PLD, after determining that the primary motherboard is connected to the secondary motherboard, sending a reply-requesting signal to the secondary PLD; C) by the secondary PLD, after receiving the reply-requesting signal, sending a reply signal corresponding to the reply-requesting signal to the primary PLD; D) by the primary PLD, after receiving the reply signal, sending an instruction to the secondary PLD; and E) by the secondary PLD, after receiving the instruction, performing an operation corresponding to the instruction.
    Type: Application
    Filed: April 27, 2023
    Publication date: April 11, 2024
    Inventors: Cyuan-Yong GAN, Yi LIN
  • Publication number: 20240120844
    Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.
    Type: Application
    Filed: April 10, 2023
    Publication date: April 11, 2024
    Inventors: Kun-Yu LIN, Ta-Yung YANG, Yu-Chang CHEN, Hsin-Yi WU, Fu-Ciao SYU, Chia-Hsien YANG
  • Publication number: 20240118316
    Abstract: A probe card and a manufacturing method of a probe card are provided. The probe card includes a probe head, first and second substrates, an insulating component, and an adhesive member. The second substrate is disposed between the probe head and the first substrate, and is disposed on the first substrate. The second substrate faces the first substrate and includes second contacts. The second contacts are electrically connected to first contacts of the first substrate. The insulating component is disposed between the first substrate and the second substrate, and disposed at an outer side of the second contacts. The adhesive member is disposed on the first substrate, arranged on at least a part of the side surface of the second substrate, and disposed at an outer side of the insulating component.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Applicant: MPI Corporation
    Inventors: Chin-Yi Lin, Che-Wei Lin, Ting-Ju Wu, Chien-Kai Hung
  • Publication number: 20240122078
    Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
  • Patent number: 11952230
    Abstract: A thick document conveying device includes a paper pickup mechanism. The paper pickup mechanism has a pick roller base, a pick roller axle, a pick roller, a switching assembly, a first universal coupling, a driving mechanism, a second universal coupling, a bearing and a gear. The pick roller axle and the pick roller are located in the pick roller base. The switching assembly is located under the pick roller base. The first universal coupling is connected to the pick roller axle. The driving mechanism is sleeved on the first universal coupling. The second universal coupling is connected to the driving mechanism. The bearing is connected to the driving mechanism. The gear is connected to the bearing. As described above, both a thick document and a thin document can be adapted.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: April 9, 2024
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: Wei Fong Lin, Yuan Yi Lin, Chih Yuan Yang
  • Patent number: 11956661
    Abstract: An uplink multi-user multi-input multi-output establishment method includes broadcasting, by a network side device, an uplink data sending announcement; receiving buffer information sent by a terminal that needs to send data, where the buffer information includes at least a sending level and a data sending length of to-be-sent data; determining, according to the buffer information, scheduling information for establishing uplink multi-user multi-input multi-output; and sending, to a terminal that is allowed to send data and selected from the terminal that needs to send data, a clear to send frame that carries the scheduling information, so that the terminal that is allowed to send data sends the to-be-sent data according to the scheduling information. The embodiments of the present disclosure effectively implement uplink multi-user multi-input multi-output establishment, so that signaling interworking is reduced, resource overheads are reduced, and data sending efficiency is improved.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: April 9, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yi Luo, Xun Yang, Yingpei Lin
  • Patent number: 11953740
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11951638
    Abstract: A method for determining a standard depth value of a marker includes obtaining a maximum depth value of the marker. A reference depth value of the marker is obtained based on a depth image of the marker, and a Z-axis coordinate value of the marker is obtained based on a color image of the marker. When the reference depth value and the Z-axis coordinate value are both less than the maximum depth value, and a difference between the reference depth value and the Z-axis coordinate value is not greater than 0, the depth reference value is set as the standard depth value of the marker; and when the difference is greater than 0, the Z-axis coordinate value is set as the standard depth value of the marker.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 9, 2024
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Tung-Chun Hsieh, Chung-Wei Wu, Chih-Wei Li, Chia-Yi Lin
  • Patent number: 11956261
    Abstract: A detection method for a malicious domain name in a domain name system (DNS) and a detection device are provided. The method includes: obtaining network connection data of an electronic device; capturing log data related to at least one domain name from the network connection data; analyzing the log data to generate at least one numerical feature related to the at least one domain name; inputting the at least one numerical feature into a multi-type prediction model, which includes a first data model and a second data model; and predicting whether a malicious domain name related to a malware or a phishing website exists in the at least one domain name by the multi-type prediction model according to the at least one numerical feature.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Acer Cyber Security Incorporated
    Inventors: Chiung-Ying Huang, Yi-Chung Tseng, Ming-Kung Sun, Tung-Lin Tsai
  • Patent number: 11956541
    Abstract: A control method of a driving mechanism is provided, including: the driving mechanism provides a first electrical signal from a control assembly to the driving mechanism to move the movable portion into an initial position relative to the fixed portion, wherein the control assembly includes a control unit and a position sensing unit; the status signal of an inertia sensing unit is read; the control unit sends the status signal to the control unit to calculate a target position; the control unit provides a second electrical signal to the driving assembly according to the target position for driving the driving assembly; a position signal is sent from the position sensing unit to the control unit; the control unit provides a third electric signal to the driving assembly to drive the driving assembly according the position signal.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: April 9, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chen-Hsien Fan, Sung-Mao Tsai, Yueh-Lin Lee, Yu-Chiao Lo, Mao-Kuo Hsu, Ching-Chieh Huan, Yi-Chun Cheng
  • Patent number: 11955347
    Abstract: One or more electronic devices that are mounted on a substrate, including at least one cooling plate in contact with the one or more electronic devices, are encapsulated. The substrate is clamped between a first mold half and a second mold half which define a molding cavity for molding the one or more electronic devices. A cavity insert movably located in the first mold half is projected into the cavity in order to contact and apply a sealing pressure onto the at least one cooling plate. After introducing a molding compound into the cavity at a first fill pressure, the molding compound in the cavity is packed by applying a second fill pressure which is higher than the first fill pressure. During this time, the sealing pressure is maintained at values that are higher than the first fill pressure and the second fill pressure.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: April 9, 2024
    Assignee: ASMPT SINGAPORE PTE. LTD.
    Inventors: Teng Hock Kuah, Yi Lin, Ravindra Raghavendra, Kar Weng Yan, Angelito Barrozo Perez
  • Patent number: 11957061
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
  • Patent number: 11951569
    Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ming Wu, Yung-Lung Lin, Hau-Yi Hsiao, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: D1023099
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: April 16, 2024
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Chia-Yi Lin, Neng-An Kuo