Patents by Inventor Yi-Shao Lai
Yi-Shao Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8072064Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance.Type: GrantFiled: June 21, 2010Date of Patent: December 6, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Publication number: 20110291690Abstract: The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on to and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening.Type: ApplicationFiled: May 20, 2010Publication date: December 1, 2011Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, I.L. Lin, Ken Juang, Ming-Hsiang Cheng
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Publication number: 20110278739Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and an interposer. The first chip is mechanically and electrically connected to the substrate. Some signal pads of the interposer are capacitively coupled to some signal pads of the first chip, so as to provide proximity communication between the first chip and the interposer. Whereby, the capacitively coupled signal pads can be made in fine pitch, and therefore the size of the semiconductor package is reduced and the density of the signal pads is increased.Type: ApplicationFiled: May 11, 2010Publication date: November 17, 2011Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Patent number: 8053906Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.Type: GrantFiled: July 10, 2009Date of Patent: November 8, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian Cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Tsung Hsu, Chih Cheng Hung
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Publication number: 20110233749Abstract: A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.Type: ApplicationFiled: March 29, 2010Publication date: September 29, 2011Inventors: Hsiao-Chuan CHANG, Tsung-Yueh TSAI, Yi-Shao LAI, Jiunn CHEN, Ming-Hsiang CHENG
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Publication number: 20110233764Abstract: A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are mechanically disposed on and electrically connected to the first surface and around the cavity, wherein the active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure, wherein the bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.Type: ApplicationFiled: March 29, 2010Publication date: September 29, 2011Inventors: Hsiao-Chuan CHANG, Tsung-Yueh Tsai, Yi-Shao Lai, Ming-Hsiang Cheng
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Publication number: 20110227212Abstract: A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a first substrate, a second substrate, two active chips, a bridge chip and a connection structure. The first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Inventors: Ming-Hsiang CHENG, Yi-Shao Lai, Tsung-Yueh Tsai, Hsiao-Chuan Chang
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Patent number: 8018075Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.Type: GrantFiled: July 10, 2009Date of Patent: September 13, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian Cheng Chen, Wei Chi Yih, Chang Ying Hung
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Patent number: 7980757Abstract: A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.Type: GrantFiled: January 8, 2009Date of Patent: July 19, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Hsiao-Chuan Chang
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Publication number: 20110156739Abstract: A test kit for testing a chip subassembly and a testing method by using the same is provided. The chip subassembly includes at least two stacked chips each having a number of electric contacts is provided. The test kit includes a test socket and a test plate. The test socket is configured to electrically engage the electric contacts on a first side of the chip subassembly. The test plate has at least a number of first probes configured for electrically engaging the electric contacts on a second side of the chip subassembly. At least one of the test socket and the test plate has a number of second probes for electrically connecting the test socket and the test plate.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Inventors: Hsiao-Chuan CHANG, Ming-Hsiang CHENG, Tsung-Yueh TSAI, Yi-Shao LAI, Ming-Kun CHEN
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Publication number: 20110156243Abstract: A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Inventors: Hsiao-Chuan CHANG, Tsung-Yueh TSAI, Yi-Shao LAI, Chang-Lin YEH, Ming-Hsiang CHENG
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Patent number: 7964949Abstract: A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.Type: GrantFiled: July 9, 2008Date of Patent: June 21, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Hsiao-Chuan Chang, Tsan-Hsien Chen
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Patent number: 7955897Abstract: A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals.Type: GrantFiled: August 8, 2008Date of Patent: June 7, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Tsung Yueh Tsai, Yi Shao Lai, Cheng Wei Huang
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Publication number: 20100007009Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.Inventors: Hsiao Chuan CHANG, Tsung Yueh TSAI, Yi Shao LAI, Ho Ming TONG, Jian Cheng CHEN, Wei Chi YIH, Chang Ying HUNG, Cheng Tsung HSU, Chih Cheng HUNG
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Publication number: 20100007011Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.Type: ApplicationFiled: July 13, 2009Publication date: January 14, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Ying HUNG, Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Jian Cheng Chen, Wei Chi Yih, Ho Ming Tong
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Publication number: 20100007010Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsiao Chuan CHANG, Tsung Yueh TSAI, Yi Shao LAI, Ho Ming TONG, Jian Cheng CHEN, Wei Chi YIH, Chang Ying HUNG
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Publication number: 20100007004Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsiao Chuan CHANG, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Wei Huang, Chih Hsing Chen, Tai Yuan Huang, Chieh Ting Chen, Yi Tsai Lu
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Publication number: 20090230564Abstract: A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals.Type: ApplicationFiled: August 8, 2008Publication date: September 17, 2009Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tsung Yueh TSAI, Yi Shao Lai, Cheng Wei Huang
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Publication number: 20090230526Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.Type: ApplicationFiled: August 15, 2008Publication date: September 17, 2009Inventors: Chien-Wen Chen, An-shih Tseng, Yi-Shao Lai, Hsiao-Chuan Chang, Tsung-Yueh Tsai
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Publication number: 20090175312Abstract: A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.Type: ApplicationFiled: January 8, 2009Publication date: July 9, 2009Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Hsiao-Chuan Chang