Abstract: A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure comprises a carrier, a chip, at least one wire, a molding compound, at least one first solder ball and at least one second solder ball. The carrier has a chip chamber passing through the first surface and the second surface. The chip is disposed in the chip chamber, and an active surface of the chip is coplanar with the first surface. During packaging, the first surface and the active surface are both tightly pasted on a carrier tape to facilitate the subsequent wire bonding and sealing process. Afterwards, the carrier tape is removed for exposing the active surface and the first surface, and the active surface of the chip is coplanar with the first surface of the carrier, hence simplifying the packaging process and reducing the thickness of the package structure.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a carrier, a chip-bonding structure and a chip. The chip-bonding structure is formed on a first surface of the carrier. The chip-bonding structure includes a cavity, a dam, several via holes and several solder bumps. The solder bumps are received in the via holes and are correspond to the first connecting pads located on the carrier. The chip is embedded in the cavity of the chip-bonding structure. An active surface of the chip is tightly pasted on the first surface of the chip-bonding structure, and the first solder pads form electrical contact with the corresponding solder bumps. The chip of the package structure is precisely disposed on the carrier, not only simplifying the manufacturing process but also forming stable electrical connection between the chip and the carrier of the package structure.

Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.

Abstract: A tensile test fixture and a tensile test method are provided. The tensile test fixture suits to perform a tensile test for a specimen. The tensile test fixture includes a base, a pull bar and a forcing member. The pull bar includes a limiting member, a specimen-fixing member and a shaft member. Wherein, the shaft member is connected between the position limiting member and the specimen-fixing member, and the specimen is fixed between the base and the specimen-fixing member. Otherwise, the forcing member has a cavity, which includes an opening. The shaft member passes through the opening, and the position limiting member is located in the cavity. The dimension of the limiting member is larger than the dimension of the opening so that the limiting member is restricted within the cavity. The forcing member is adopted to pull the limiting member to perform a tensile test for the specimen.

Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.

Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.

Abstract: A bonding strength test device suits to perform a bonding strength test for at least one solder ball that fixed on a substrate. The bonding strength test device includes a fixed base and an impact apparatus. The impact apparatus has a first end and a second end corresponding to the first end. While an impact is applied to the first end of the impact apparatus, the impact apparatus moves downward, and the second end of the impact apparatus hits the solder ball on the substrate for performing the bonding strength test. Besides, the fixed base is used for limiting the downward movement of the impact apparatus.

Abstract: A tensile test fixture and a tensile test method are provided. The tensile test fixture suits to perform a tensile test for a specimen. The tensile test fixture includes a base, a pull bar and a forcing member. The pull bar includes a limiting member, a specimen-fixing member and a shaft member. Wherein, the shaft member is connected between the position limiting member and the specimen-fixing member, and the specimen is fixed between the base and the specimen-fixing member. Otherwise, the forcing member has a cavity, which includes an opening. The shaft member passes through the opening, and the position limiting member is located in the cavity. The dimension of the limiting member is larger than the dimension of the opening so that the limiting member is restricted within the cavity. The forcing member is adopted to pull the limiting member to perform a tensile test for the specimen.

Abstract: A stacked chip package is provided. The metal bumps disposed on the lower chip are encapsulated by a layer of non-conductive adhesive and the area around by the layer of non-conductive adhesive material is filled with another adhesive. Under such a configuration, it can prevent the upper chip from contacting the bonding wires connected to the lower chip and eliminate the fracture of the upper chip during the wire bonding process.

Abstract: A chip manufacturing process is disclosed. A wafer having a passivation layer and at least one bonding pad is provided. The surface of the bonding pad is exposed to a first opening of the passivation layer. A first metal layer is formed on the bonding pad exposed by the first opening. A photoresist having a second opening and a photoresist block disposed in the second opening is formed on the first metal layer. The first metal layer corresponding to the second opening has a first surface, and the first metal layer corresponding to the photoresist block has a second surface. A second metal layer is formed on the first surface, and the photoresist block is removed to expose the second surface. A UBM layer is formed on the second metal layer and the second surface of the first metal layer. Finally, a conductive bump is formed on the UBM layer.

Abstract: A bonding strength test device suits to perform a bonding strength test for at least one solder ball that fixed on a substrate. The bonding strength test device includes a fixed base and an impact apparatus. The impact apparatus has a first end and a second end corresponding to the first end. While an impact is applied to the first end of the impact apparatus, the impact apparatus moves downward, and the second end of the impact apparatus hits the solder ball on the substrate for performing the bonding strength test. Besides, the fixed base is used for limiting the downward movement of the impact apparatus.

Abstract: A tensile test fixture and a tensile test method are provided. The tensile test fixture suits to perform a tensile test for a specimen. The tensile test fixture includes a base, a pull bar and a forcing member. The pull bar includes a limiting member, a specimen-fixing member and a shaft member. Wherein, the shaft member is connected between the position limiting member and the specimen-fixing member, and the specimen is fixed between the base and the specimen-fixing member. Otherwise, the forcing member has a cavity, which includes an opening. The shaft member passes through the opening, and the position limiting member is located in the cavity. The dimension of the limiting member is larger than the dimension of the opening so that the limiting member is restricted within the cavity. The forcing member is adopted to pull the limiting member to perform a tensile test for the specimen.

Abstract: An asymmetric bump structure for wafer is provided. First, the wafer includes multi-chip units each of which has an active surface. The asymmetric bump structure includes a conductive surface on the active surface, a conductive structure contacted the portion of the conductive surface and located on the both conductive surface and the active surface, and a conductive material contacted the conductive structure. The conductive material and the conductive structure contacted part of the conductive surface have respective geometric centers which are not on an identical vertical axis.

Abstract: A chip package includes a package substrate, a chip and a molding compound. The package substrate has a carrying surface and a back surface opposite to the carrying surface. The chip is mounted on the carrying surface and electrically connected to the package substrate. Furthermore, the molding compound is applied over the carrying surface to cover the chip and a part of the package substrate. The outline of a juncture between the molding compound and the package substrate is a smooth closed curve so that thermal stress is uniformly distributed over the juncture to prevent stress concentration. The reliability of the package structure is thereby improved.

Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.