Patents by Inventor Yi Wei

Yi Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11962328
    Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: April 16, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
  • Publication number: 20240118199
    Abstract: An optical analysis system and an optical analysis method, which simply change driving electric currents of light-emitting units via using a control and process unit, so that a wavelength range and a peak wavelength of an irradiated light generated by each light-emitting unit may be fine-tuned. A plurality of irradiating lights with different wavelength ranges and peak wavelengths are irradiated to the object to be tested in different times, so that merely fewer light-emitting units may be used to improve a detection resolution and a detection accuracy of a spectrum of the object to be tested.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 11, 2024
    Applicant: MEGA CRYSTAL BIOTECHNOLOGY SINGAPORE PTE. LTD.
    Inventors: Yi-Sheng Ting, Kuo-Wei Hsu
  • Publication number: 20240120030
    Abstract: The present application provides a method for analyzing droplets on the basis of volume distribution including obtaining a total volume V of a sample containing target molecules based on a system prepared using the sample. The system is emulsified into droplets. A droplet system is obtained when the droplets obtaining the sample executes an amplification reaction. A droplet image of the droplet system is obtained. A total number n of droplets included in the droplet system is obtained based on the droplet image. A droplet volume distribution of the droplet system is obtained based on the droplet image. A number j of negative droplets among the n droplets is counted. A quantitative analysis is performed for the target molecules according to the total volume V of the sample, the total number n of droplets, the droplet volume distribution information, and the number j of negative droplets.
    Type: Application
    Filed: January 13, 2021
    Publication date: April 11, 2024
    Inventors: YUN XIA, XIA ZHAO, YANG XI, YI WEI, FANG CHEN, HUI JIANG
  • Publication number: 20240117840
    Abstract: A slide rail assembly adapted to dispose to a first casing is provided. The slide rail assembly includes an outer slide rail, an inner slide rail, and first and second engaging components. The outer slide rail includes a first hook. The inner slide rail is slidably disposed to the outer slide rail and includes first and second ends and positioning slots. First fixing portions of the first casing is engaged with several of the positioning slots. The first engaging component is partially overlapped with a critical positioning slot of the positioning slots and includes a second hook. The second engaging component includes a third hook. When the first casing is set on the inner slide rail, the second hook leaves an engaging path with the first hook, and the first casing and the inner slide rail slide to a position where the third hook is engaged with the first hook.
    Type: Application
    Filed: August 9, 2023
    Publication date: April 11, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Yi-Ching Tseng, Chih-Wei Yu
  • Publication number: 20240120203
    Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.
    Type: Application
    Filed: March 8, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
  • Publication number: 20240120632
    Abstract: A coupler for use in a wireless communication device includes a signal input end, a signal output end, a coupling end, an isolation end, a main signal hole, and a first coupling hole disposed on a PCB. A first end of the main signal hole is coupled to the signal input end. A second end of the main signal hole is coupled to the signal output end. A first end of the first coupling hole is coupled to the coupling end. A second end of the first coupling hole is coupled to the isolation end. In a thickness direction of the PCB, the first end of the first coupling hole and the first end of the main signal hole are close to a first side of the PCB, and the second end of the first coupling hole and the second end of the main signal hole are close to a second side of the PCB.
    Type: Application
    Filed: December 16, 2023
    Publication date: April 11, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Peng Gao, Xianlin Wei, Youbing Pan, Yi Xu
  • Patent number: 11951233
    Abstract: Provided are methods of producing an acellular organ. The method includes the steps of, subjecting an organ derived from an animal to a static supercritical fluid (SCF) treatment followed by a dynamic SCF treatment. Optionally, the method of the present disclosure further includes a hypertonic and a hypotonic treatments prior to the static SCF treatment, and/or a neutralizing treatment after the dynamic SCF treatment. Also disclosed herein are acellular organs produced by the present method.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 9, 2024
    Assignee: ACRO BIOMEDICAL COMPANY. LTD.
    Inventors: Dar-Jen Hsieh, Chao-Yi Wei, Chao-Chin Chao, Jer-Cheng Kuo, Yi-Ping Lai, Srinivasan Periasamy
  • Patent number: 11953774
    Abstract: A display substrate includes: a base substrate (100); a plurality of sub-pixels (R, G, B) located on the base substrate (100), every two rows of sub-pixels (R, G, B) constituting a pixel group; a plurality of first gate lines (Gate1) located at first row gaps between the pixel groups, two first gate lines (Gate1) being arranged at each first row gap; and a plurality of photosensors (101), the orthographic projection of each row of photosensors (101) on the base substrate (100) completely covering a second row gap in the pixel group and partially overlapping with the orthographic projections of the sub-pixels (R, G, B), thereby avoiding the bright and dark difference between adjacent rows and ensuring the aperture ratio.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: April 9, 2024
    Assignees: Beijing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xinlan Yang, Wenkai Mu, Yi Liu, Jun Fan, Bo Feng, Yang Wang, Zhan Wei, Tengfei Ding, Shijun Wang, Chengfu Xu
  • Patent number: 11955329
    Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Patent number: 11955154
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • Patent number: 11954441
    Abstract: A device and method for generating article markup information are provided. The method for generating article markup information includes the following. Segmentation processing is performed on an article to generate a segmentation result. Name entity recognition is performed on the segmentation result to generate a first recognition result. Whether the segmentation result includes any word in an expansion list is determined. Expanded entity classification conversion is performed on the first recognition result to generate a second recognition result. The second recognition result and the segmentation result are used as markup information.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: April 9, 2024
    Assignee: Acer Incorporated
    Inventors: Yi-Chun Lin, Yueh-Yarng Tsai, Pin-Cyuan Lin, Ke-Han Pan, Sheng-Wei Chu
  • Publication number: 20240109193
    Abstract: A method includes, during a processing cycle: navigating the sanding head across a region of a workpiece according to a toolpath; and, based on a sequence of force values output by a force sensor coupled to the sanding head, deviating the sanding head from the toolpath to maintain forces of the sanding head on the workpiece region proximal a target force. The method also includes: detecting a sequence of positions of the sanding head traversing the workpiece region; interpreting a surface contour in the workpiece region based on the sequence of positions; detecting a difference between the surface contour and a corresponding target surface defined in a target model of the workpiece; generating a second toolpath for the workpiece region based on the difference; and, during a second processing cycle, navigating the sanding head across the workpiece region according to the second toolpath to reduce the difference.
    Type: Application
    Filed: December 12, 2023
    Publication date: April 4, 2024
    Inventors: Avadhoot L. Ahire, Yi-Wei Chen, Satyandra K Gupta, Ariyan M. Kabir, Ashish Kulkarni, Ceasar G. Navarro, JR., Martin G. Philo, Brual C. Shah
  • Publication number: 20240114487
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives, in a first slot and from a base station, a first signal that is a downlink data signal in a first frequency resource allocation. The UE communicates, with the base station, a second signal in a second slot. A configured time gap between the first slot and the second slot is according to a comparison of the first frequency resource allocation and a second frequency resource allocation.
    Type: Application
    Filed: September 19, 2023
    Publication date: April 4, 2024
    Inventors: Chiou-Wei TSAI, Wei-De WU, Yi-Chia LO, Tien-Shin HO
  • Publication number: 20240113113
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20240113032
    Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 4, 2024
    Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
  • Patent number: 11944814
    Abstract: A wireless implant and associated system for motor function recovery after spinal cord injury, and more particularly a multi-channel wireless implant with small package size. The wireless implant can further be used in various medical applications, such as retinal prostheses, gastrointestinal implant, vagus nerve stimulation, and cortical neuromodulation. The system also includes a method and its implementation to acquire the impedance model of the electrode-tissue interface of the implant.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 2, 2024
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Yi-Kai Lo, Wentai Liu, Victor R. Edgerton, Chih-Wei Chang
  • Patent number: 11948938
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Publication number: 20240107121
    Abstract: Computer-implemented systems and methods for livestream engagement enhancement are disclosed and may be configured to retrieve a first set of texts; retrieve a second set of texts; transmit a plurality of texts including at least the first and second set of texts for display on one or more user interfaces associated with one or more user devices; receive user interaction data from at least one of the one or more user devices, wherein the user interaction data includes indication of user interaction by one or more users with at least one or more texts of the plurality of texts via at least one of the one or more user interfaces; and transmit each text of the one or more texts to a second user device for display on at least one of a first page or a second page of a second user interface.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Applicant: COUPANG CORP.
    Inventors: Yi CAO, Xin WEI, Jun HANG, Wei LUO