Patents by Inventor Yi-Chen Wang

Yi-Chen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150803
    Abstract: A non-human organism for upgrading intermediate oxidation products formed by catalytic degradation of alkanes or polystyrenes is provided. The non-human organism is genetically modified to convert the intermediate oxidation products to secondary metabolites, and in particular to include a positive feedback loop construction in the promotor system. A method includes steps of catalytically degrading alkanes or polystyrene in an oxidizing environment to form intermediate products with one or more catalysts and contacting the intermediate products with the non-human organism such that intermediate oxidation products are converted to secondary metabolites.
    Type: Application
    Filed: October 16, 2023
    Publication date: May 9, 2024
    Applicants: UNIVERSITY OF SOUTHERN CALIFORNIA, UNIVERSITY OF KANSAS
    Inventors: Berl OAKLEY, Travis J. WILLIAMS, Yi-Ming CHIANG, Clay C. WANG, Yuhao CHEN, Swati BIJLANI, C. Elizabeth OAKLEY, Christian Anthony RABOT
  • Publication number: 20240154520
    Abstract: A power factor correction (PFC) converter comprises an inductor, a main switch, a voltage divider, a diode, and a controller. The main switch controls the inductor performing magnetization and demagnetization, wherein a voltage difference between two ends of the main switch is a switch voltage. The voltage divider divides the switch voltage and generates a division voltage. The controller performs the following operations periodically in general mode: turning on the main switch; turning off the main switch after the main switch is turned on for a period of time; obtaining the switch voltage according to the division voltage, and determining the period of time for which the main switch is turned on next time according to the switch voltage and a predetermined output voltage of the PFC converter; and obtaining an output voltage according to the switch voltage during a period of time after the main switch is turned off.
    Type: Application
    Filed: March 30, 2023
    Publication date: May 9, 2024
    Applicant: Diodes Incorporated
    Inventors: Haoming Chen, Yi-Chun Wang, Koyen Lee, Feng-Jung Huang
  • Patent number: 11977232
    Abstract: A wearable device and a method for adjusting a display state based on an environment are provided. The method is adapted for the wearable device. The method includes: capturing an environmental image; when determining that there is a specific object in the environmental image, determining a display mode of a display circuit based on the specific object; and controlling the display circuit to be adjusted to a display state corresponding to the display mode.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: May 7, 2024
    Assignee: Coretronic Corporation
    Inventors: Shih-Min Wu, Yi-Fa Wang, Ping-Chen Ma
  • Patent number: 11965217
    Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 23, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yi-Chen Li, Chih-Cheng Tsou, Min-Hsien Wu, Hsin-Yao Wang, Chien-Ru Lin
  • Patent number: 11967622
    Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Publication number: 20240129012
    Abstract: A wearable device includes a frame element and a dielectric substrate. The frame element includes a first metal element, a second metal element, and a third metal element. A first gap is provided between the first metal element and the second metal element. A second gap is provided between the second metal element and the third metal element. A third gap is provided between the third metal element and the first metal element. The dielectric substrate is surrounded by the first metal element, the second metal element, and the third metal element. A first antenna element is formed by the first metal element. A second antenna element is formed by the second metal element. A third antenna element is formed by the third metal element.
    Type: Application
    Filed: December 6, 2022
    Publication date: April 18, 2024
    Inventors: Jing-Yao XU, Chung-Ting HUNG, Chun-Yuan WANG, Chu-Yu TANG, Yi-Chih LO, Yu-Chen ZHAO, Chih-Tsung TSENG
  • Patent number: 11962296
    Abstract: Disclosed herein is a flexible sensing interface, comprising: a sensor, comprising: a core; an inner electrode in the form of a conductive material in contact with the core; an inner dielectric material substantially encasing the inner electrode; an outer electrode in the form of a conductive material in contact with the inner dielectric material and in electrical communication with the inner electrode; and an outer dielectric material substantially encasing the outer electrode; wherein the inner dielectric material and the outer dielectric material comprise an elastic material. Also disclosed herein are systems and methods for making and using the same.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: April 16, 2024
    Assignee: Georgia Tech Research Corporation
    Inventors: Seyedeh Fereshteh Shahmiri, Chaoyu Chen, Gregory D. Abowd, Shivan Mittal, Thad Eugene Starner, Yi-Cheng Wang, Zhong Lin Wang, Dingtian Zhang, Steven L. Zhang, Anandghan Waghmare
  • Patent number: 11961893
    Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 11950431
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: April 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
  • Publication number: 20240102328
    Abstract: A hinge device includes a pivot seat, a rotating shaft, a first friction block, and a locking assembly. By being structurally provided with a sleeve, a first cam ring, a first elastic ring, a second friction block, a second cam ring, a second elastic ring, an elastic element, a locking portion, and a cover of the locking assembly, the hinge device has a locking function and a long service life.
    Type: Application
    Filed: July 10, 2023
    Publication date: March 28, 2024
    Inventors: Chun-Fu CHANG, Hui-Chen WANG, Yi-Chun TANG
  • Publication number: 20240079409
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. A first width direction of the first conductive contact structure is substantially parallel to a second width direction of the first conductive via structure.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyun-De WU, Te-Chih HSIUNG, Yi-Chun CHANG, Yi-Chen WANG, Yuan-Tien TU, Peng WANG, Huan-Just LIN
  • Patent number: 11916471
    Abstract: An example electronic device includes a controller to determine a user touch detection by a power adaptor coupled to the electronic device to operate the electronic device in an AC power mode. The power adaptor may comprise a proximity sensor to detect a user touch for detachment of the power adaptor from the electronic device, and a control circuit to operate a configuration pin in a low output mode to signal user touch detection. The controller may initiate central processing unit (CPU) throttling to reduce power consumption by the electronic device. The controller may further stop CPU throttling in response to detecting that the power adaptor has been detached from the electronic device. Further, the controller may switch the electronic device to a DC power mode to operate using DC power supplied by a battery of the electronic device in response to power adaptor detachment.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: February 27, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ting-Yang Tsai, Yi-Chen Chen, Ching-Lung Wang, Yu-Min Shen
  • Patent number: 11915379
    Abstract: The disclosure provides a display image adjustment method and an augmented reality display device. The display image adjustment method includes the following steps. Received image data is converted to a coordinate system of the augmented reality display device to obtain initial coordinate information. An initial image is provided to an active display region of the augmented reality display device based on the initial coordinate information. The initial coordinate information is adjusted in a virtual adjustment coordinate region to obtain adjusted coordinate information when an adjustment command is received. An adjusted image is provided to the active display region of the augmented reality display device based on the adjusted coordinate information. The display image adjustment method and the augmented reality display device proposed by the disclosure may adjust display content of the AR display device according to user's needs.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: February 27, 2024
    Assignee: Coretronic Corporation
    Inventors: Shih-Min Wu, Yi-Fa Wang, Ping-Chen Ma
  • Patent number: 11823850
    Abstract: An information handling system keyboard backlight illuminates with a single mini-LED disposed under each of plural keyboard keys and having a penta directional illumination that illuminates directly at the key and coplanar a light guide material around the perimeter of the mini-LED. The light guide material in cooperation with a reflector below and a mask above provides indirect illumination at the periphery of the key for a more uniform key illumination. A substrate carried with circuits below the mini-LED powers the mini-LED so that a more bulky flexible printed circuit is not needed.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: November 21, 2023
    Assignee: Dell Products L.P.
    Inventors: Wen-Pin Huang, Hsien-Tsan Chang, Yi-Chen Wang, Po-Chun Hou
  • Publication number: 20230361185
    Abstract: A device comprises a source/drain contact over a source/drain region of a transistor, an etch stop layer above the source/drain contact, an interlayer dielectric (ILD) layer above the etch stop layer, and a source/drain via extending through the ILD layer and the etch stop layer to the source/drain contact. The etch stop layer has an oxidized region in contact with the source/drain via and separated from the source/drain contact.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih HSIUNG, Yi-Chun CHANG, Yi-Chen WANG, Yuan-Tien TU, Huan-Just LIN, Jyun-De WU
  • Patent number: 11810919
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. The first conductive via structure has a first substantially strip shape in a top view of the first conductive via structure.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyun-De Wu, Te-Chih Hsiung, Yi-Chun Chang, Yi-Chen Wang, Yuan-Tien Tu, Peng Wang, Huan-Just Lin
  • Publication number: 20230298934
    Abstract: A semiconductor device includes a gate structure, source/drain regions, source/drain contacts, a gate dielectric cap, an etch stop layer, and a gate contact. The gate structure is over a substrate. The source/drain regions are at opposite sides of the gate structure. The source/drain contacts are over the source/drain regions, respectively. The gate dielectric cap is over the gate structure and has opposite sidewalls interfacing the source/drain contacts.
    Type: Application
    Filed: April 20, 2023
    Publication date: September 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih HSIUNG, Yi-Chun CHANG, Jyun-De WU, Yi-Chen WANG, Yuan-Tien TU, Huan-Just LIN
  • Patent number: 11749732
    Abstract: A method comprises forming a source/drain contact over a source/drain region; forming an etch stop layer over the source/drain contact and an interlayer dielectric (ILD) layer over the etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and a recess in the etch stop layer; oxidizing a sidewall of the recess in the etch stop layer; after oxidizing the sidewall of the recess in the etch stop layer, performing a second etching process to extend the via opening down to the source/drain contact; and after performing the second etching process, forming a source/drain via in the via opening.
    Type: Grant
    Filed: February 6, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih Hsiung, Yi-Chun Chang, Yi-Chen Wang, Yuan-Tien Tu, Huan-Just Lin, Jyun-De Wu
  • Patent number: 11664272
    Abstract: A method comprises forming a gate structure over a semiconductor substrate; forming an etch stop layer over the gate structure and an ILD layer over the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, resulting in a sidewall of the etch stop layer being exposed in the gate contact opening; oxidizing the exposed sidewall of the etch stop layer; after oxidizing the exposed sidewall of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih Hsiung, Yi-Chun Chang, Jyun-De Wu, Yi-Chen Wang, Yuan-Tien Tu, Huan-Just Lin
  • Publication number: 20230061072
    Abstract: The invention discloses an astaxanthin (AST) nanoemulsion and its manufacturing method. The manufacturing method comprising steps of: adding an AST material into a peanut oil and mixing them uniformly to obtain an AST oil; adding 0.25-1.5 (w/w)% of a surfactant into the AST oil and mixing them uniformly to obtain a mixed solution; and adding water into the mixed solution to obtain an AST emulsion precursor; and shaking the AST emulsion precursor to obtain the AST nanoemulsion.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 2, 2023
    Inventors: HUI-MIN WANG, JUI-JEN CHANG, HSING-YU HUANG, YI-CHEN WANG