Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

Abstract: Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, aiid removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the tunneling region.

Abstract: The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.

Abstract: The MOS transistor of the present invention is manufactured by a conventional complementary MOS transistor technology. In the manufacturing method of the MOS transistor having nanometer dimensions, a gate having dimensions at a nanometer scale can be formed through control of the width of spacers instead of with a specific lithography technology. The doped spacers are used for forming source/drain extension regions having an ultra-shallow junction, thereby avoiding damage on the substrate caused by ion implantation. In addition, a dopant is diffused from the doped space into a semiconductor substrate through annealing to form the source/drain extension regions having an ultra-shallow junction.

Abstract: Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, and removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the tunneling region.

Abstract: The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit.

Abstract: A level shifter for generating a plurality of output voltages having a plurality of levels to interface a low voltage circuit with a high voltage circuit is provided. The level shifter includes a first level shifter for receiving an input signal and a first power supply through a load transistor and outputting a first output voltage having a level the same as that of a ground voltage or the first power supply according to the input signal, a first control signal having a value in which the first output voltage is inverted, and a second control signal having the same value as that of the first output voltage, and an output voltage generator for receiving the first power supply and a second power supply having a level different from that of the first power supply and outputting a second output voltage having a level equivalent to either the first power supply or the second power supply according to the first and second control signals.

Abstract: The present invention relates to a ferroelectric memory cell array formed of a single transistor, and method of storing data using the same. The ferroelectric memory cell array includes a plurality of word lines connected to gates of the memory cells located at respective rows, a plurality of bit lines connected to drains of the memory cells located at respective columns, a common source line commonly connecting sources of the memory cells, and a plurality of well lines each connected to wells in which the memory cells are each formed, wherein a bias voltage of an unit pulse shape is applied to a gate of a selected memory cell and a bias voltage of a pulse shape is applied to a well line. Therefore, the present invention allows a random access without a disturbance since data can be written by means of the polarity characteristic of the ferroelectric.

Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

Abstract: The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate.

Abstract: The present invention relates to a ferroelectric memory cell array formed of a single transistor, and method of storing data using the same. The ferroelectric memory cell array includes a plurality of word lines connected to gates of the memory cells located at respective rows, a plurality of bit lines connected to drains of the memory cells located at respective columns, a common source line commonly connecting sources of the memory cells, and a plurality of well lines each connected to wells in which the memory cells are each formed, wherein a bias voltage of an unit pulse shape is applied to a gate of a selected memory cell and a bias voltage of a pulse shape is applied to a well line. Therefore, the present invention allows a random access without a disturbance since data can be written by means of the polarity characteristic of the ferroelectric.

Abstract: An apparatus for forming Strontium-Tantalum-Oxide films and a method thereof using an atomic layer deposition tool are provided. In the Strontium-Tantalum-Oxide films deposited by using plasma and the atomic layer deposition, its leakage-current is very low, and its dielectric constant has a range of 30 to 100 depending on the there heating conditions. Therefore, the method provides structures for i) an insulating film of an NDRO-type ferroelectric memory device that has a structure of Metal-film/Ferroelectric-film/Insulating-film/Silicon, ii) a gate oxide film substituting for silicon oxide film, and iii) an insulating film of Electro Luminescent Display (ELD) device.

Abstract: A ferroelectric memory device including a single ferroelectric transistor that one unit memory cell is independently selected and programmed, when the unit memory cell is programmed for “the first state” or “the second state” by applying a DC bias voltage to the single ferroelectric transistor's gate and well. In addition, the ferroelectric memory device can be applied with normal power level Vdd and GND. The ferroelectric memory device includes a plurality of unit memory cells which are arranged in a matrix, by crossing at least one word line in a column direction with a plurality of bit lines and source lines in a row direction and is connected between the source line and the bit line.

Abstract: An apparatus for forming Strontium-Tantalum-Oxide films and a method thereof using an atomic layer deposition tool are provided. In the Strontium-Tantalum-Oxide films deposited by using plasma and the atomic layer deposition, its leakage-current is very low, and its dielectric constant has a range of 30 to 100 depending on the there heating conditions. Therefore, the method provides structures for i) an insulating film of an NDRO-type ferroelectric memory device that has a structure of Metal-film/Ferroelectric-film/Insulating-film/Silicon, ii) a gate oxide film substituting for silicon oxide film, and iii) an insulating film of Electro Luminescent Display (ELD) device.

Abstract: A serial communication interface is provided in which the data length operating mode is selectable. Based on the selected data length operating mode, serial-to-parallel and/or parallel-to-serial conversion takes place in data blocks of the selected data length.

Abstract: A reference voltage generation circuit which is capable of generating a reference voltage having multiple steps by using a periodic response characteristic of a chaotic circuit. The circuit includes a first sample/hold unit for sampling and holding a periodic output voltage V3 in accordance with a first clock signal CLK1 from an externally connected clock signal generation unit, a second sample/hold unit for sampling and holding an output voltage V3' from the first sample/hold unit in accordance with a second clock signal CLK2 from the externally connected clock signal generation unit, a non-linear unit for receiving voltage V4 from the second sample/hold unit and outputting a non-linear voltage V2 signal having a sawtooth-shaped transfer characteristic, and an addition unit for adding the non-linear voltage signal V2 from the non-linear unit and an externally applied voltage signal V1 and outputting the periodic output voltage V3.

Abstract: A non-linear circuit includes a first variable resistor one end of which is applied with an input signal, an amplifier whose inverting input is connected to the other end of the first variable resistor and whose non-inverting input is connected to ground, a second variable resistor one end of which is connected to the inverting input of the amplifier, a third variable resistor one end of which is connected to the output of the amplifier and the other end being connected to the other end of the second variable resistor, and a fourth variable resistor one end of which is applied with the input signal and the other end being connected to the third variable resistor.