Abstract: A spin-transfer-torque magnetoresistive memory comprises apparatus and method of manufacturing a three terminal magnetoresistive memory element having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell comprises a bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current along the SHE-metal layer by applying a low write current.

Abstract: A method to make magnetic random access memory (MRAM), in particular, perpendicular spin transfer torque MRAM or p-STT-MRAIVI is provided. Electrically isolated memory cell is formed by ion implantation instead of etching and dielectric refill. Oxygen ion implantation is used to convert the photolithography exposed areas into metal oxide dielectric matrix. An ultrathin single-layer or multiple-layer of oxygen-getter, selected from Mg, Zr, Y, Th, Ti, Al, Ba is inserted into the active magnetic memory layer in addition to putting a thicker such material above and below the memory layer to effectively capture the impinged oxygen ions. Oxygen is further confined within the core device layer by adding oxygen stopping layer below the bottom oxygen-getter.

Abstract: Present invention discloses a perpendicular STT-MRAM, a method of operating, and a method of manufacturing the same and a plurality of magnetoresistive memory elements having a recording layer which has an interface interaction with an underneath dielectric functional layer. The energy switch barrier of the recording layer is reduced under an electric field applying along a perpendicular direction of the functional with a proper voltage on a digital line from a control circuitry; accordingly, the perpendicular magnetization of the recording layer is readily reversible in a low spin-transfer switching current.

Abstract: A method of making a magnetoresistive element comprises making a crystalline structural quality and magnetic anisotropy enhancement bilayer (CSMAE bilayer) thus a). enhancing the crystalline structural quality, hence fabrication yield, of the resulting magnetoresistive element; and b). enhancing the magnetic anisotropy of the recording layer whereby achieving a high MR ratio for the magnetoresistive element with a simultaneous reduction of an undesirable spin pumping effect. As the magnetoresistive film is thermally annealed, a crystallization process occurs to form bcc CoFe grains having epitaxial growth with (100) plane parallel to the surface of the tunnel barrier layer as Boron elements migrate into the impurity absorbing layer.

Abstract: Present invention includes an apparatus of and method of making a spin-transfer-torque magnetoresistive memory with three terminal magnetoresistive memory element(s) having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell has a bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current along the SHE-metal layer by applying a low write current.

Abstract: A planar STT-MRAM includes apparatus, made by a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a ferromagnetic recording layer forming a flux closure with a self-aligned ferromagnetic soft adjacent layer which has an electric field enhanced perpendicular anisotropy through an interface interaction with a dielectric functional layer. The energy switch barrier of the soft adjacent layer is reduced under an electric field along a perpendicular direction with a proper voltage on a digital line from a control circuitry; accordingly, the in-plane magnetization of the recording layer is readily reversible in a low spin-transfer switching current.

Abstract: A STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having a dielectric thermal buffer layer between a thin top electrode of the MTJ element and a bit line, and a bit-line VIA electrically connecting the top electrode and the bit line having a vertical distance away from the location of the MTJ stack. In a laser thermal annealing, a short wavelength of a laser has a shallow thermal penetration depth and a high thermal resistance from the bit line to the MTJ stack only causes a temperature rise of the MTJ stack being much smaller than that of the bit line. As the temperature of the MTJ element during the laser thermal annealing of bit line copper layer is controlled under 300-degree C., possible damages on MTJ and magnetic property can be avoided.

Abstract: A perpendicular magnetoresistive element comprises anovel buffer layer provided on a surface of the recording layer, which is opposite to a surface of the recording layer where the tunnel barrier layer is provided, wherein at least the portion of the buffer layer interfacing to the recording layer contains a rocksalt crystal structure having the (100) plane parallel to the substrate plane and at least a portion of the buffer layer comprises a doped element having conductivity enhancement and the perpendicular resistance of the buffer layer is relatively small than that of the tunnel barrier layer. The invention preferably includes materials, configurations and processes of perpendicular magnetoresistive elements suitable for perpendicular spin-transfer torque MRAM applications.

Abstract: A method to make magnetic random access memory with extremely small cell size is provided. Using atomic layer deposition (ALD) technique, a very thin film of hard mask material is uniformly grown on the vertical spatial walls of a pre-form. Stand alone hard mask is formed after removing the pre-form. Array of magnetic memory cells are formed by reactive ion etch (RIE) or ion milling using such small hard mask. This way, the dimension of the hard mask is no longer limited by photolithography tool capability, instead, it is controlled by ALD-grown hard mask film thickness which can be made extremely thin.

Abstract: This invention is about a method to make three-terminal spin transfer torque transistor magnetic random access memory (ST3-MRAM) cell using plasma based ion implantation. The core memory stack of such ST3-MRAM cell contains a bottom digit line (or VIA), a thick dielectric insulating layer, a memory layer, another thin dielectric layer, and a magnetic reference layer on the top. After the formation of the top magnetic reference pillar by photolithography patterning and etching, the outside region of the magnetic memory layer is converted to a non-magnetic conducting lead by heavy doping of boron ions generated by plasma from boron hydrogen (BxH3x) containing gas.

Abstract: This invention is to make a three-terminal perpendicular spin transfer torque magnetic random access memory (pSTT-MRAM) with a magnetic reference layer at bottom. The first electrode (digital line) is connected to a magnetic reference layer at the bottom, and the second electrode is located at the middle memory layer which is connected to the underneath CMOS circuit through VIA and the third electrode is a voltage gate connecting to the top bit line which is used to reduce the write current when a voltage is applied between the top and middle electrode.

Abstract: A planar STT-MRAM comprises apparatus, a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a ferromagnetic recording layer forming a flux closure with a self-aligned ferromagnetic soft adjacent layer which has an electric field enhanced perpendicular anisotropy through an interface interaction with a dielectric functional layer. The energy switch barrier of the soft adjacent layer is reduced under an electric field along a perpendicular direction with a proper voltage on a digital line from a control circuitry; accordingly, the in-plane magnetization of the recording layer is readily reversible in a low spin-transfer switching current.

Abstract: A magnetic sensor with increased sensitivity, lower noise, and improved frequency response is described. The sensor's free layer is ribbon shaped and is closely flanked at each long edge by a ribbon of magnetically soft, high permeability material. The side stripes of soft magnetic material absorb external field flux and concentrate the flux to flow into the sensor's edges to promote larger MR sensor magnetization rotation. The free layer may be deposited simultaneously with the soft magnetic layer when they are aligned in the same plane. When the flux absorbing stripes are positioned above or below the MR sensor, then the free layer and flux absorbing stripes are deposited in separate steps.

Abstract: A magnetic sensor with increased sensitivity, lower noise, and improved frequency response is described. The sensor's free layer is ribbon shaped and is closely flanked at each long edge by a ribbon of magnetically soft, high permeability material. Side stripes of soft magnetic material absorb external field flux and concentrate the flux to flow into the sensor's edges to promote larger MR sensor magnetization rotation. Side stripes may be located in the plane of the free layer a maximum distance of 0.1 microns, above a plane that includes a free layer top surface, or below a plane that includes the magnetic sensor bottom surface. Edges of each side stripe may be aligned above or below a portion of the magnetic sensor. Moreover, each side stripe may have a tapered edge such that the side stripes have increasing thickness with increasing distance from the magnetic sensor.

Abstract: A STT-MRAM comprises a method to form magnetic random access memory (MRAM) element array having ultra small dimensions using double photo exposures and etch of their hard masks. The memory cells are located at the cross section of two ultra-narrow photo-resist lines suspended between two large photo-resist bases. Array of MRAM cells with small dimension is formed by a third magnetic etch.

Abstract: This invention is about a three-terminal spin transistor magnetic random access memory and the method to make it with a narrow foot print. The first terminal, a bit line, is connected to the top magnetic reference layer, and the second terminal is located at the middle memory layer which is connected to the underneath CMOS control circuit through VIA and the third one, a digital line, is a voltage gate with a narrow point underneath the memory layer across an insulating layer which is used to reduce the write current when it is turned on. The fabrication includes formation of a large VIA base, formation of digital line, formation of memory cell & VIA connection and formation of the top bit line. Dual photolithography patterning and hard mask etch are used to form the digital line pillar and small memory pillar.

Abstract: A method to form a small magnetic random access memory (MRAM) cell using collimated oxygen ion implantation is provided. With a proper control of the bias voltage and collimation angle, oxygen ions are impinged into the magnetic memory layers with a desired energy and bombardment angle, yielding a sharp oxygen boundary around the memory cell. After a high temperature anneal, a dielectric matrix with good metal-oxide bonding is formed within the oxygen implanted memory region and thus forming a small MRAM cell in the mask protected area.

Abstract: A magnetic sensor with increased sensitivity, lower noise, and improved frequency response is described. The sensor's free layer is ribbon shaped and is closely flanked at each long edge by a ribbon of magnetically soft, high permeability material. The side stripes of soft magnetic material absorb external field flux and concentrate the flux to flow into the sensor's edges to promote larger MR sensor magnetization rotation. Side stripes may be located in the plane of the free layer a maximum distance of 0.1 microns, above a plane that includes a top surface of the free layer, or below a plane that includes the bottom surface of the magnetic sensor. Edges of each side stripe may be aligned above or below a portion of the magnetic sensor.

Abstract: A STT-MRAM comprises apparatus, and method of operating a double-MTJ magnetoresistive memory and a plurality of magnetoresistive memory element having a first recording layer which has an interface interaction with an underneath dielectric functional layer and having a second recording layer which has no interface interaction with an underneath dielectric functional layer. The energy switch barrier of the first recording layer is reduced under an electric field applying along a perpendicular direction of the functional with a proper voltage on a digital line from a control circuitry; accordingly, the magnetization of the first recording layer is readily reversible in a low spin-transfer switching current while the magnetization of the second recording layer is readily reversible in a high spin-transfer switching current, enabling two separate bits recording in a double MTJ stack.

Abstract: A STT-MRAM comprises apparatus and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of a three-terminal magnetoresistive memory element having a voltage-gated recording. A bit line is coupled to the memory element through an upper electrode provided on the top surface of a reference layer, a select CMOS is coupled to the recording layer of the memory element through a middle second electrode and a VIA and a digital line is coupled to a voltage gate which is insulated from the recording layer by a dielectric layer and is used to adjust the switching write current. The fabrication includes formation of bottom digital line, formation of memory cell & VIA connection, formation of top bit line. Dual photolithography patterning and hard mask etch are used to form a small memory pillar. Ion implantation is used to convert a buried dielectric VIA into an electrical conducting path between middle memory cell and underneath CMOS device.