Patents by Inventor Ying-Chih Lin
Ying-Chih Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113187Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Jhu-Min Song, Ying-Chou Chen, Yi-Kai Ciou, Chien-Chih Chou, Fei-Yun Chen, Yu-Chang Jong, Chi-Te Lin
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Publication number: 20240100743Abstract: A separation apparatus suitable for separating plastic and silicone in a composite material includes a storage tank configured to store a hydrocarbon solvent, and a reaction tank fluidly connected to the storage tank and having a reaction space for placement of the composite material therein and for receiving the hydrocarbon solvent from the storage tank such that the composite material is immersed in the hydrocarbon solvent for separating the plastic and the silicone in the composite material. The plastic and the silicone in the composite material are insoluble in the hydrocarbon solvent.Type: ApplicationFiled: September 19, 2023Publication date: March 28, 2024Applicants: Taiwan Green Point Enterprises Co., Ltd., Jabil Circuit (Singapore) Pte. Ltd.Inventors: Bing-Yuan Lin, Ying-Yin Chen, Yung-Chih Chen, Ching-Hsin Chen
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Patent number: 11545547Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.Type: GrantFiled: May 12, 2021Date of Patent: January 3, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Ching Chang, Kai-Lou Huang, Ying-Chih Lin, Gang-Yi Lin
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Patent number: 11364548Abstract: The present disclosure provides a gripper module, including a base, an adapter holder, a collet holder, and an actuator. The base is adapted for an adapter to be detachably disposed thereon. The adapter holder is able to engage and to buckle the adapter. The collet holder is able to engage and to buckle a collet which is installed in the adapter. The actuator is connected to the collet holder. The actuator can pull the collet holder and the collet to move, causing pressing and retraction of the collet by the conical surface between the collet and the adapter. Therefore, sizes of collets may apply to the gripper module with the adapter. By sheathing the adapter, replacement and size alternation of the collets are made easier, and precisions of allocations of the collet and the gripped workpiece are improved.Type: GrantFiled: September 8, 2020Date of Patent: June 21, 2022Assignee: Agile Wing Smart Manufacturing Co., Ltd.Inventors: Hung-Wu Lee, Yong-Lin Chen, Ying-Chih Lin
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Publication number: 20210265462Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.Type: ApplicationFiled: May 12, 2021Publication date: August 26, 2021Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Ching Chang, Kai-Lou Huang, Ying-Chih Lin, Gang-Yi Lin
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Publication number: 20210220926Abstract: The present disclosure provides a gripper module, including a base, an adapter holder, a collet holder, and an actuator. The base is adapted for an adapter to be detachably disposed thereon. The adapter holder is able to engage and to buckle the adapter. The collet holder is able to engage and to buckle a collet which is installed in the adapter. The actuator is connected to the collet holder. The actuator can pull the collet holder and the collet to move, causing pressing and retraction of the collet by the conical surface between the collet and the adapter. Therefore, sizes of collets may apply to the gripper module with the adapter. By sheathing the adapter, replacement and size alternation of the collets are made easier, and precisions of allocations of the collet and the gripped workpiece are improved.Type: ApplicationFiled: September 8, 2020Publication date: July 22, 2021Inventors: Hung-Wu Lee, Yong-Lin Chen, Ying-Chih Lin
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Patent number: 11038014Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.Type: GrantFiled: October 8, 2018Date of Patent: June 15, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Ching Chang, Kai-Lou Huang, Ying-Chih Lin, Gang-Yi Lin
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Patent number: 10825684Abstract: Provided is a material composition and method for that includes providing a substrate and forming a resist layer over the substrate. In various embodiments, the resist layer includes a multi-metal complex including an extreme ultraviolet (EUV) absorption element and a bridging element. By way of example, the EUV absorption element includes a first metal type and the bridging element includes a second metal type. In some embodiments, an exposure process is performed to the resist layer. After performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.Type: GrantFiled: January 6, 2017Date of Patent: November 3, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Hao Chang, Chien-Chih Chen, Kuo-Chang Kau, Jeng-Horng Chen, Pi-Yeh Chia, Chi-Ren Chen, Ying-Chih Lin
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Patent number: 10795255Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.Type: GrantFiled: October 31, 2018Date of Patent: October 6, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Wei-Lun Hsu, Gang-Yi Lin, Yu-Hsiang Hung, Ying-Chih Lin, Feng-Yi Chang, Ming-Te Wei, Shih-Fang Tzou, Fu-Che Lee, Chia-Liang Liao
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Patent number: 10734284Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.Type: GrantFiled: September 19, 2018Date of Patent: August 4, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin, Chieh-Te Chen, Yi-Ching Chang
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Publication number: 20200212048Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.Type: ApplicationFiled: January 27, 2019Publication date: July 2, 2020Inventors: Gang-Yi Lin, Shih-Fang Tzou, Fu-Che Lee, Feng-Yi Chang, Ying-Chih Lin, Kai-Lou Huang, Yi-Ching Chang
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Patent number: 10700071Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.Type: GrantFiled: January 27, 2019Date of Patent: June 30, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Gang-Yi Lin, Shih-Fang Tzou, Fu-Che Lee, Feng-Yi Chang, Ying-Chih Lin, Kai-Lou Huang, Yi-Ching Chang
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Patent number: 10672612Abstract: The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.Type: GrantFiled: May 3, 2018Date of Patent: June 2, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Gang-Yi Lin, Feng-Yi Chang, Ying-Chih Lin, Fu-Che Lee
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Patent number: 10658178Abstract: A method of forming a capacitor mask includes the following steps. A bulk mandrel and a plurality of strip mandrels are formed on a mask layer. Spacers are formed on sidewalls of the bulk mandrel and the strip mandrels. The strip mandrels are removed while the bulk mandrel is reserved. A material fills in space between the spacers and on the bulk mandrel, wherein the material has a flat top surface. A patterned photoresist is formed to cover the bulk mandrel and a part of the spacers but exposing the other part of the spacers after filling the material.Type: GrantFiled: July 1, 2018Date of Patent: May 19, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin
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Publication number: 20200105764Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.Type: ApplicationFiled: October 31, 2018Publication date: April 2, 2020Inventors: Wei-Lun Hsu, Gang-Yi Lin, Yu-Hsiang Hung, Ying-Chih Lin, Feng-Yi Chang, Ming-Te Wei, Shih-Fang Tzou, Fu-Che Lee, Chia-Liang Liao
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Publication number: 20200083325Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.Type: ApplicationFiled: October 8, 2018Publication date: March 12, 2020Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Ching Chang, Kai-Lou Huang, Ying-Chih Lin, Gang-Yi Lin
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Patent number: 10535530Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.Type: GrantFiled: October 22, 2018Date of Patent: January 14, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin
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Publication number: 20190385847Abstract: A method of forming a capacitor mask includes the following steps. A bulk mandrel and a plurality of strip mandrels are formed on a mask layer. Spacers are formed on sidewalls of the bulk mandrel and the strip mandrels. The strip mandrels are removed while the bulk mandrel is reserved. A material fills in space between the spacers and on the bulk mandrel, wherein the material has a flat top surface. A patterned photoresist is formed to cover the bulk mandrel and a part of the spacers but exposing the other part of the spacers after filling the material.Type: ApplicationFiled: July 1, 2018Publication date: December 19, 2019Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin
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Patent number: 10475662Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.Type: GrantFiled: October 12, 2018Date of Patent: November 12, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Wei-Hsin Liu, Ying-Chih Lin, Jui-Min Lee, Gang-Yi Lin, Fu-Che Lee
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Publication number: 20190311901Abstract: The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.Type: ApplicationFiled: May 3, 2018Publication date: October 10, 2019Inventors: Gang-Yi Lin, Feng-Yi Chang, Ying-Chih Lin, Fu-Che Lee