Patents by Inventor Ying-Chih Lin
Ying-Chih Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190304777Abstract: The present invention provides a method for fabricating a hard mask, comprising: firstly, a first material layer and a second material layer are provided on the first material layer, a cell region and a peripheral region are defined thereon, and then a plurality of sacrificial patterns and a plurality of spacers are formed in the cell region on the second material layer, each two spacers are located at two sides of each of the sacrificial patterns. Afterwards, a first etching step is performed to remove the sacrificial patterns, a second etching step is performed to remove a portion of the second material layer and expose a portion of the first material layer within the cell region, and a third etching step is performed to remove portions of the first material layer, so as to forma plurality of first recesses in the first material layer.Type: ApplicationFiled: April 26, 2018Publication date: October 3, 2019Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin
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Patent number: 10354876Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate and a material layer. The substrate has a first region, and the material layer is disposed on the substrate. The material layer includes plural of first patterns and plural of second patterns arranged in an array, and two third patterns. The first patterns are disposed within the first region, the second patterns are disposed at two opposite outer sides of the first region, and the third patterns are disposed at another two opposite outer sides of the first region, wherein each of the third patterns partially merges each of a part of the first patterns and each of a part of the second patterns.Type: GrantFiled: June 24, 2018Date of Patent: July 16, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee, Ying-Chih Lin
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Publication number: 20190181014Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.Type: ApplicationFiled: October 22, 2018Publication date: June 13, 2019Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin
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Publication number: 20190172722Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.Type: ApplicationFiled: October 12, 2018Publication date: June 6, 2019Inventors: Feng-Yi Chang, Wei-Hsin Liu, Ying-Chih Lin, Jui-Min Lee, Gang-Yi Lin, Fu-Che Lee
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Patent number: 10312088Abstract: A self-aligned double patterning method includes the steps of forming line structures spaced apart from each other in a first direction on a mask layer, forming dielectric layer on the line structures, performing an etch back process so that the top surfaces of the line structures and the dielectric layer are flush, forming layer structure with same material as the line structures on the line structures and the dielectric layer, forming spacers spaced apart from each other in a second direction on the layer structure, and performing an etch process with the spacers as an etch mask to pattern the line structures and the dielectric layer.Type: GrantFiled: February 20, 2018Date of Patent: June 4, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin
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Publication number: 20190139824Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.Type: ApplicationFiled: September 19, 2018Publication date: May 9, 2019Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin, Chieh-Te Chen, Yi-Ching Chang
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Patent number: 10192825Abstract: A semiconductor device includes a first gate line, a second gate line and a first bar-shaped contact structure. The first gate line has a first long axis extending along a first direction. The second gate line is parallel to the first gate line. The first bar-shaped contact structure has a second axis forming an angle substantially greater than 0° and less than 90° with the first long axis.Type: GrantFiled: November 28, 2017Date of Patent: January 29, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Hao Huang, Chun-Lung Chen, Kun-Yuan Liao, Ying-Chih Lin, Chia-Lin Lu
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Publication number: 20170271150Abstract: Provided is a material composition and method for that includes providing a substrate and forming a resist layer over the substrate. In various embodiments, the resist layer includes a multi-metal complex including an extreme ultraviolet (EUV) absorption element and a bridging element. By way of example, the EUV absorption element includes a first metal type and the bridging element includes a second metal type. In some embodiments, an exposure process is performed to the resist layer. After performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.Type: ApplicationFiled: January 6, 2017Publication date: September 21, 2017Inventors: Shu-Hao CHANG, Chien-Chih CHEN, Kuo-Chang KAU, Jeng-Horng CHEN, Pi-Yeh CHIA, Chi-Ren CHEN, Ying-Chih LIN
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Patent number: 9312365Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.Type: GrantFiled: September 16, 2014Date of Patent: April 12, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
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Patent number: 9013024Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.Type: GrantFiled: October 15, 2013Date of Patent: April 21, 2015Assignee: United Microelectronics Corp.Inventors: Ying-Chih Lin, Hsuan-Hsu Chen, Jiunn-Hsiung Liao, Lung-En Kuo
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Publication number: 20150004766Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
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Patent number: 8872280Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.Type: GrantFiled: July 31, 2012Date of Patent: October 28, 2014Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
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Publication number: 20140038417Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.Type: ApplicationFiled: October 15, 2013Publication date: February 6, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ying-Chih Lin, Hsuan-Hsu Chen, Jiunn-Hsiung Liao, Lung-En Kuo
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Publication number: 20140035066Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
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Patent number: 8592322Abstract: A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.Type: GrantFiled: June 28, 2012Date of Patent: November 26, 2013Assignee: United Microelectronics Corp.Inventors: Feng-Yi Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin, Po-Chao Tsao
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Patent number: 8461649Abstract: An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.Type: GrantFiled: September 16, 2011Date of Patent: June 11, 2013Assignee: United Microelectronics Corp.Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Feng-Yi Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin
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Publication number: 20130093062Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Inventors: Ying-Chih Lin, Hsuan-Hsu Chen, Jiunn-Hsiung Liao, Lung-En Kuo
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Publication number: 20120270403Abstract: A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.Type: ApplicationFiled: June 28, 2012Publication date: October 25, 2012Inventors: Feng-Yi Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin, Po-Chao Tsao
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Patent number: 8293639Abstract: A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.Type: GrantFiled: February 16, 2009Date of Patent: October 23, 2012Assignee: United Microelectronics Corp.Inventors: Feng-Yih Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin
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Patent number: 8236702Abstract: A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.Type: GrantFiled: March 5, 2008Date of Patent: August 7, 2012Assignee: United Microelectronics Corp.Inventors: Feng-Yi Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin, Po-Chao Tsao