Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

Abstract: Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and performs a first coarse valley tracking calibration operation on the segment of the memory array. The control logic further configures a read voltage level and one or more parameters associated with the read operation based on a result of the first coarse valley tracking calibration operation and performs a second fine valley tracking calibration operation on the segment of the memory array using the configured read voltage level and the configured one or more parameters.

Abstract: Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line.

Abstract: A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. During a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. A pass through read voltage level associated with the target wordline is identified. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

Abstract: Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.

Abstract: A memory device comprising a memory array and control logic operatively coupled with the memory array. The control logic is to: detect a program operation directed at a selected wordline of multiple wordlines of the memory array; determine, during an initial phase of the program operation, whether a program voltage being applied to the selected wordline satisfies a threshold program voltage; add, in response to the program voltage not satisfying the threshold program voltage, a base offset voltage to an initial pass voltage to generate a higher pass voltage, the initial pass voltage being a percentage of an initial program voltage; and cause the higher pass voltage to be applied to a remainder of the multiple wordlines other than the selected wordline.

Abstract: A device might include a common source, a three-dimensional array of memory cells, a plurality of access lines, and a controller. The three-dimensional array of memory cells might include a plurality of NAND strings. Each NAND string might be selectively connected between a corresponding data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings. The controller might be configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.

Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

Abstract: A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.

Abstract: Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.

Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

Abstract: Control logic in a memory device initiates, subsequent to a program verify phase of a program operation, a new program operation on the memory array, the new program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causing one or more positive pre-boosting voltages to be applied to corresponding subsets of a plurality of word lines of a block of the memory array during the pre-boosting phase and causes the one or more positive pre-boosting voltages to be ramped down to a ground voltage during the pre-boosting phase in a designated order based on a location of the corresponding subsets of the plurality of word lines to which the one or more positive pre-boosting voltages were applied.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.