Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

Abstract: A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.

Abstract: Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.

Abstract: A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

Abstract: A device might include a common source, a three-dimensional array of memory cells, a plurality of access lines, and a controller. The three-dimensional array of memory cells might include a plurality of NAND strings. Each NAND string might be selectively connected between a corresponding data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings. The controller might be configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.

Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data block of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

Abstract: Control logic in a memory device initiates, subsequent to a program verify phase of a program operation, a new program operation on the memory array, the new program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causing one or more positive pre-boosting voltages to be applied to corresponding subsets of a plurality of word lines of a block of the memory array during the pre-boosting phase and causes the one or more positive pre-boosting voltages to be ramped down to a ground voltage during the pre-boosting phase in a designated order based on a location of the corresponding subsets of the plurality of word lines to which the one or more positive pre-boosting voltages were applied.

Abstract: A memory might include a common source, a first data line and a second data line, an array of memory cells, a plurality of access lines, and a controller. The array of memory cells might include a first string of memory cells selectively connected between the first data line and the common source and a second string of memory cells selectively connected between the second data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of the first string of memory cells and a control gate of a respective memory cell of the second string of memory cells. The controller may access the array of memory cells. The controller might be configured to implement a source-side seeding operation concurrently with a data line set operation.

Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

Abstract: A processing device in a memory system initiates a program operation on the memory device, the program operation comprising a seeding phase. The processing device further causes a seeding voltage to be applied to a string of memory cells in a data block of the memory device during the seeding phase of the program operation and causes a positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase. Each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causes a first positive pre-boosting voltage to be applied to a first plurality of word lines of a data block of the memory array during the pre-boosting phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

Abstract: A memory might include a common source, a first data line and a second data line, an array of memory cells, a plurality of access lines, and a controller. The array of memory cells might include a first string of memory cells selectively connected between the first data line and the common source and a second string of memory cells selectively connected between the second data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of the first string of memory cells and a control gate of a respective memory cell of the second string of memory cells. The controller may access the array of memory cells. The controller might be configured to implement a source-side seeding operation concurrently with a data line set operation.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches. The line trenches laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction. Each line trench fill structure includes a laterally undulating dielectric rail having a laterally undulating width along the second horizontal direction and extending along the first horizontal direction and a row of memory stack structures located at neck regions of the laterally undulating dielectric rail.