Patents by Inventor Yohei Hasegawa

Yohei Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210006952
    Abstract: A sever transmits an acknowledgement in response to data transmission from first and second terminals, respectively, among a plurality of terminals. The server controls the first and second terminals so that the first and second terminals open a reception slot at substantially the same timing. The server transmits a collective acknowledgement shared by the first and second terminals during both of the first and second terminals open the reception slot.
    Type: Application
    Filed: March 28, 2019
    Publication date: January 7, 2021
    Applicant: NEC CORPORATION
    Inventor: Yohei HASEGAWA
  • Patent number: 10871901
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: December 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Patent number: 10853321
    Abstract: A storage system includes non-volatile storage devices and a control device. Each of the storage devices is divided into blocks, and data is erased in units of the blocks. The control device includes a setting unit and a writing/reading unit. The setting unit sets first storage regions obtained by dividing a storage region for each of the storage devices and sets second storage regions obtained by dividing storage regions of all of the storage devices for all of the storage devices. The writing/reading unit manages data stored in the storage devices in units of the second storage regions. The setting unit sets each of the first storage regions so that the first storage region for at least one of the plurality of storage devices includes the entirety of one or more blocks and sets each of the second storage regions to include two or more of the first storage regions.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yohei Hasegawa, Yoshiki Saito, Shohei Onishi, Hidenori Matsuzaki, Shigehiro Asano
  • Publication number: 20200221389
    Abstract: A communication control device 30 that determines second communication processing that is communication processing that can be executed in parallel with first communication processing that is communication processing that is executed between a transmission terminal and a reception terminal. The communication control device including: a transmission power determination unit 31 that determines conditions for the transmission power of a signal that would not impede the first communication processing, even if a signal that is transmitted by means of the second communication processing is received by the reception terminal; and a destination determination unit 32 that determines a destination for the second communication processing from among terminals at which a signal that is transmitted at transmission power that satisfies the determined conditions could arrive.
    Type: Application
    Filed: July 11, 2018
    Publication date: July 9, 2020
    Applicant: NEC Corporation
    Inventor: Yohei HASEGAWA
  • Publication number: 20200089617
    Abstract: According to one embodiment, a memory system includes a cache configured to cache a part of a multi-level mapping table for logical-to-physical address translation, and a controller. The multi-level mapping table includes a plurality of hierarchical tables corresponding to a plurality of hierarchical levels. The table of each hierarchical level includes a plurality of address translation data portions. The controller sets a priority for each of the hierarchical level based on a degree of bias of reference for each of the hierarchical level, and preferentially caches each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with low priority.
    Type: Application
    Filed: March 11, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei ONISHI, Yoshiki SAITO, Yohei HASEGAWA, Konosuke WATANABE
  • Patent number: 10573985
    Abstract: Terminals 40, 50 involving stationary-side retained portions 44, 54 are held in place by stationary housings, movable-side retained portions 42, 52 are held in place by a movable housing, and resilient portions 43, 53 are provided between said stationary-side retained portions 44, 54 and movable-side retained portions 42, 52. In the above-mentioned housing, in the terminal array direction, retaining fittings 60 are attached at locations outside said terminal array range, the above-mentioned retaining fittings 60 include mounting portions 61 fixedly attached to the housing and retaining portions 62 that clamp and hold the counterpart connector component. The retaining portions 62 of said retaining fittings 60 clamp and hold the above-mentioned counterpart connector component, thereby maintaining the locations of contact between the contact portions of the above-mentioned terminals 40, 50 and the above-mentioned counterpart connector component.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 25, 2020
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Yohei Hasegawa, Takahiro Abe
  • Publication number: 20200028631
    Abstract: A receive terminal setting a non-delivery determination time for determining that a next data packet is not delivered after transmitting an acknowledgement (ACK) packet for a received data packet; when the next data packet is not delivered within the non-delivery determination time, the receive terminal repeatedly transmits a retransmission request (RACK) packet prompting the transmission of the next data packet; a transmit terminal specifies a non-delivered data packet using time difference information based on the time-of-day information of the received ACK packet and RACK packet and retransmits the specified data packet to the receive terminal; the time-of-day information here is a time stamp added by the receive terminal to each of the ACK packet and RACK packet when transmitted, or a time stamp added by the transmit terminal to each of the ACK packet and RACK packet when received.
    Type: Application
    Filed: February 20, 2018
    Publication date: January 23, 2020
    Applicant: NEC Corporation
    Inventor: Yohei HASEGAWA
  • Publication number: 20200008197
    Abstract: A communication apparatus is provided with a communication part, a response index calculation part, and a determination part. The communication part is configured to be capable of transmitting a packet to the terminal, via frequency carrier(s) of a base station to which the terminal is connected. The response index calculation part calculates a response index of the packet. The determination part determines the number of frequency carrier(s) used by the terminal in accordance with the result of the response index calculation by the response index calculation part. Determining a number of frequency carriers being used includes determining the number of LTE carrier waves being used by the terminal.
    Type: Application
    Filed: September 26, 2017
    Publication date: January 2, 2020
    Applicant: NEC CORPORATION
    Inventors: Tansheng LI, Yohei HASEGAWA, Takeo ONISHI, Takahiro NOBUKIYO
  • Patent number: 10483670
    Abstract: Electrical connector for circuit boards provided with terminals having connecting portions configured to be connected to a circuit board at one end in the longitudinal direction of said terminals and contact portions configured to be placed in contact with a counterpart connector component at the other end, and a housing holding a plurality of said terminals in place in array form. Said housing having disposed therein the contact portions of the terminals, and formed such that it is divided into a receiving-side housing, which accommodates the contact portions and receives a counterpart connector component such that it is placed in contact with the contact portions, and a board-side housing, which holds the terminals in place in sections more proximal to the connecting portions than to the contact portions and which is mounted to a circuit board, and the receiving-side housing and the board-side housing are molded as a single unit.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 19, 2019
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Yohei Hasegawa, Takahiro Abe
  • Patent number: 10483674
    Abstract: A connector with stationary housings, a movable housing, and terminals. The terminals have a movable-side retained portion including a contact portion secured in place by unitary molding in a movable-side retaining portion of the movable housing, a stationary-side retained portion secured in place by unitary molding at a location proximate the connecting portion of the terminals in a stationary-side retaining portion of the stationary housing, and a resiliently displaceable resilient portion coupling the movable-side retained portion to the stationary-side retained portion. The resilient portion has a curved apex portion constituting the upper end of the resilient portion outwardly of the movable-side retained portion in the connector-width direction, and lateral open spaces, which are open in the connector-width direction, are formed in a range including at least the apex portion below the above-mentioned movable-side retaining portion positioned above the apex portion.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: November 19, 2019
    Assignee: Hirose Electric Co., Ltd.
    Inventor: Yohei Hasegawa
  • Patent number: 10418731
    Abstract: Terminals 40 including stationary-side retained portions are held in place by stationary housings 20, movable-side retained portions are held in place by a movable housing 30, and resilient portions are provided between said stationary-side retained portions and movable-side retained portions, and, in the movable housing 30, abutment portions 72 of abutment fittings are provided on the bottom face that faces the circuit board, thereby facilitating the above-mentioned abutment portions 72 to abut the surface of the circuit board when the movable housing 30 moves towards the circuit board.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: September 17, 2019
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventors: Yohei Hasegawa, Takahiro Abe
  • Publication number: 20190199833
    Abstract: In order to enable a delay until the output of retransmission data to be reduced, performing transfer of a data piece that is input from a data input unit to a first transfer unit, performing determination of necessity of retransmission of the data piece, when the retransmission is determined to be necessary, performing transfer of a retransmission data piece that is necessary to be retransmitted to a second transfer unit, and in advance of at least any of the data piece remaining in the first transfer unit at a point of time of the transfer of the retransmission data piece to the second transfer unit, performing output of the retransmission data piece in the second transfer unit to a same destination as that of the data piece in the first transfer unit.
    Type: Application
    Filed: May 15, 2017
    Publication date: June 27, 2019
    Applicant: NEC CORPORATION
    Inventor: Yohei HASEGAWA
  • Patent number: 10283886
    Abstract: Stationary housings 20 involve stationary-side reinforcing fittings 80 secured in place in said stationary housings 20 via integral molding with said stationary housings 20 and, moreover, a movable housing involves movable-side reinforcing fittings 60, 70 secured in place in said movable housing 30 via integral molding with said movable housing. The stationary-side reinforcing fittings 80 involve exposed portions 82 exposed from the stationary housings 20 at locations outside the terminal array range of said terminals in the terminal array direction, and the movable-side reinforcing fittings 60, 70 involve expanded portions 63, 73 protruding from the movable housing 30 at locations outside the above-mentioned array range.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: May 7, 2019
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventors: Yohei Hasegawa, Takahiro Abe
  • Publication number: 20190107947
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Patent number: 10230187
    Abstract: A connector with stationary housings, a movable housing, and terminals. The terminals have a movable-side retained portion including a contact portion secured in place by unitary molding in a movable-side retaining portion of the movable housing, a stationary-side retained portion secured in place by unitary molding at a location proximate the connecting portion of the terminals in a stationary-side retaining portion of the stationary housing, and a resiliently displaceable resilient portion coupling the movable-side retained portion to the stationary-side retained portion. The resilient portion has a curved apex portion constituting the upper end of the resilient portion outwardly of the movable-side retained portion in the connector-width direction, and lateral open spaces, which are open in the connector-width direction, are formed in a range including at least the apex portion below the above-mentioned movable-side retaining portion positioned above the apex portion.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 12, 2019
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventor: Yohei Hasegawa
  • Publication number: 20190052003
    Abstract: Terminals 40, 50 involving stationary-side retained portions 44, 54 are held in place by stationary housings, movable-side retained portions 42, 52 are held in place by a movable housing, and resilient portions 43, 53 are provided between said stationary-side retained portions 44, 54 and movable-side retained portions 42, 52. In the above-mentioned housing, in the terminal array direction, retaining fittings 60 are attached at locations outside said terminal array range, the above-mentioned retaining fittings 60 include mounting portions 61 fixedly attached to the housing and retaining portions 62 that clamp and hold the counterpart connector component. The retaining portions 62 of said retaining fittings 60 clamp and hold the above-mentioned counterpart connector component, thereby maintaining the locations of contact between the contact portions of the above-mentioned terminals 40, 50 and the above-mentioned counterpart connector component.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 14, 2019
    Inventors: Yohei HASEGAWA, Takahiro ABE
  • Publication number: 20190052002
    Abstract: Terminals 40 including stationary-side retained portions are held in place by stationary housings 20, movable-side retained portions are held in place by a movable housing 30, and resilient portions are provided between said stationary-side retained portions and movable-side retained portions, and, in the movable housing 30, abutment portions 72 of abutment fittings are provided on the bottom face that faces the circuit board, thereby facilitating the above-mentioned abutment portions 72 to abut the surface of the circuit board when the movable housing 30 moves towards the circuit board.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 14, 2019
    Inventors: Yohei HASEGAWA, Takahiro ABE
  • Publication number: 20190052005
    Abstract: Stationary housings 20 involve stationary-side reinforcing fittings 80 secured in place in said stationary housings 20 via integral molding with said stationary housings 20 and, moreover, a movable housing involves movable-side reinforcing fittings 60, 70 secured in place in said movable housing 30 via integral molding with said movable housing. The stationary-side reinforcing fittings 80 involve exposed portions 82 exposed from the stationary housings 20 at locations outside the terminal array range of said terminals in the terminal array direction, and the movable-side reinforcing fittings 60, 70 involve expanded portions 63, 73 protruding from the movable housing 30 at locations outside the above-mentioned array range.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 14, 2019
    Inventors: Yohei HASEGAWA, Takahiro ABE
  • Publication number: 20190052004
    Abstract: Electrical connector for circuit boards provided with terminals having connecting portions configured to be connected to a circuit board at one end in the longitudinal direction of said terminals and contact portions configured to be placed in contact with a counterpart connector component at the other end, and a housing holding a plurality of said terminals in place in array form. Said housing having disposed therein the contact portions of the terminals, and formed such that it is divided into a receiving-side housing, which accommodates the contact portions and receives a counterpart connector component such that it is placed in contact with the contact portions, and a board-side housing, which holds the terminals in place in sections more proximal to the connecting portions than to the contact portions and which is mounted to a circuit board, and the receiving-side housing and the board-side housing are molded as a single unit.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 14, 2019
    Inventors: Yohei HASEGAWA, Takahiro ABE
  • Patent number: 10180795
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 15, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito