Patents by Inventor Yohei Hasegawa

Yohei Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10171348
    Abstract: A communications control device that, if a communications failure occurs at location in a first path for communications that extends across a plurality of communications layers, selects any second path from a candidate group including at least one second path for continuing communications without going via the location where the communications failure has occurred, on the basis of the time required for each second path to switch from the first path to the second path, and sends, to a communications device for performing the switching, an instruction for switching the first path to the selected second path and continuing communications.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: January 1, 2019
    Assignee: NEC CORPORATION
    Inventors: Yohei Hasegawa, Atsushi Iwata
  • Publication number: 20180366853
    Abstract: A connector with stationary housings, a movable housing, and terminals. The terminals have a movable-side retained portion including a contact portion secured in place by unitary molding in a movable-side retaining portion of the movable housing, a stationary-side retained portion secured in place by unitary molding at a location proximate the connecting portion of the terminals in a stationary-side retaining portion of the stationary housing, and a resiliently displaceable resilient portion coupling the movable-side retained portion to the stationary-side retained portion. The resilient portion has a curved apex portion constituting the upper end of the resilient portion outwardly of the movable-side retained portion in the connector-width direction, and lateral open spaces, which are open in the connector-width direction, are formed in a range including at least the apex portion below the above-mentioned movable-side retaining portion positioned above the apex portion.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 20, 2018
    Inventor: Yohei HASEGAWA
  • Publication number: 20180203615
    Abstract: According to one embodiment, a storage control device has, as a unit of storage, a stripe including one or more chunks being storage areas included in any of a plurality of storages. The storage control device includes a first selector, a divider, and a determiner. The first selector is configured to select a stripe from a plurality of stripes on the basis of the number of one or more pieces of valid first data included in the stripe. The divider is configured to divide the chunk included in the stripe selected by the first selector into a plurality of partial chunks. The determiner is configured to determine the partial chunk that is to be a target of garbage collection on the basis of the number of one or more pieces of the valid first data included in the partial chunk.
    Type: Application
    Filed: September 12, 2017
    Publication date: July 19, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiki SAITO, Yohei HASEGAWA, Shohei ONISHI, Hidenori MATSUZAKI, Shigehiro ASANO
  • Publication number: 20180143992
    Abstract: A storage system includes non-volatile storage devices and a control device. Each of the storage devices is divided into blocks, and data is erased in units of the blocks. The control device includes a setting unit and a writing/reading unit. The setting unit sets first storage regions obtained by dividing a storage region for each of the storage devices and sets second storage regions obtained by dividing storage regions of all of the storage devices for all of the storage devices. The writing/reading unit manages data stored in the storage devices in units of the second storage regions. The setting unit sets each of the first storage regions so that the first storage region for at least one of the plurality of storage devices includes the entirety of one or more blocks and sets each of the second storage regions to include two or more of the first storage regions.
    Type: Application
    Filed: September 12, 2017
    Publication date: May 24, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Yohei HASEGAWA, Yoshiki SAITO, Shohei ONISHI, Hidenori MATSUZAKI, Shigehiro ASANO
  • Publication number: 20180138618
    Abstract: A connector with stationary housings, a movable housing, and terminals. The terminals have a movable-side retained portion including a contact portion secured in place by unitary molding in a movable-side retaining portion of the movable housing, a stationary-side retained portion secured in place by unitary molding at a location proximate the connecting portion of the terminals in a stationary-side retaining portion of the stationary housing, and a resiliently displaceable resilient portion coupling the movable-side retained portion to the stationary-side retained portion. The resilient portion has a curved apex portion constituting the upper end of the resilient portion outwardly of the movable-side retained portion in the connector-width direction, and lateral open spaces, which are open in the connector-width direction, are formed in a range including at least the apex portion below the above-mentioned movable-side retaining portion positioned above the apex portion.
    Type: Application
    Filed: November 1, 2017
    Publication date: May 17, 2018
    Inventor: Yohei HASEGAWA
  • Publication number: 20180107389
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Application
    Filed: December 19, 2017
    Publication date: April 19, 2018
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Patent number: 9906437
    Abstract: A communication system includes a control apparatus that controls communication apparatus(s) included in a hierarchical network, and a first communication apparatus that forms links in a first layer of the network and performs processing related to communication flows based on a first packet handling operation. The control apparatus determines destinations to accommodate communication flows specified according to the first packet handling operation, based on information related to a second layer that differs from the first layer.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: February 27, 2018
    Assignee: NEC Corporation
    Inventors: Yohei Hasegawa, Yohei Iizawa
  • Patent number: 9891837
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: February 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Patent number: 9769856
    Abstract: A communication system includes a communication control apparatus that establishes a communication path between terminals and notifies at least one of the terminals of information about the established communication path. The terminal that has received the notification from the communication control apparatus establishes a communication protocol to be used for communication between the terminals on the basis of the information from the communication control apparatus.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: September 19, 2017
    Assignee: NEC CORPORATION
    Inventor: Yohei Hasegawa
  • Patent number: 9690682
    Abstract: A program information generating system includes an acquisition unit that acquires dependency information indicating dependency among a plurality of events generated by execution of a program and selection information identifying a selected event that is the event selected by a user; a generation unit that generates display information, on the basis of the dependency information and the selection information, such that a dependency path that is formed of the plurality of events having the dependency and includes the selected event is displayed in a distinguishable manner; and a display control unit that controls a display unit, on the basis of the display information, such that a display image indicating an execution state of the program is displayed.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: June 27, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Kuroda, Yohei Hasegawa, Hidenori Matsuzaki, Nobuaki Tojo, Mayuko Koezuka
  • Patent number: 9569355
    Abstract: According to an embodiment, a memory system includes multiple nonvolatile memories to/from each of which data can be written/read independently of one another; and a controller configured to control writing of data to and reading of data from the nonvolatile memories. Each of the nonvolatile memories includes a data storage including a normal data storage area for storing the data and a redundant data storage area for writing the data avoiding defect positions in the normal data storage area; and a defect information storage configured to store defect information indicating information on a defect of the data storage included in another nonvolatile memory different from the present nonvolatile memory.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yohei Hasegawa, Shigehiro Asano, Tokumasa Hara
  • Patent number: 9544223
    Abstract: A communication system includes: a plurality of nodes each of which is configured to include OAM (Operation Administration and Maintenance) functions; and a control apparatus configured to control the plurality of nodes. Each of the nodes transmits a status change notification including information about a port(s) affected by a failure(s) that has occurred in a network composed by the plurality of nodes to the control apparatus. The control apparatus determines whether to perform route control on the network on the basis of the status change notification and information about a composition of the network.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: January 10, 2017
    Assignee: NEC CORPORATION
    Inventors: Masahiro Hayashitani, Yohei Hasegawa
  • Patent number: 9450318
    Abstract: In the terminals of the first electrical connector, the elastic arm portions are formed such that their width dimensions in the array direction of the above-mentioned terminals are smaller than the securing arm portions; in the terminals of the second electrical connector, the sections that correspond to the securing arm portions are formed such that their width dimensions are smaller than the sections that correspond to the elastic arm portions; on the elastic arm portions side, the terminals of the first electrical connector are formed such that their width dimensions are smaller than the terminals of the second electrical connector; and on the securing arm portions side, the terminals of the second electrical connector are formed such that their width dimensions are smaller than the terminals of the first electrical connector.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 20, 2016
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventor: Yohei Hasegawa
  • Publication number: 20160266827
    Abstract: A memory controller that controls data transfer performed between a memory device and another memory device, the memory controller includes: an acquiring unit that acquires command information which contains first address information indicating a first memory area to be accessed during the data transfer; a determining unit that determines whether the first memory area belongs to a specific external address space which represents a specific address space in an external memory; and a converting unit that, when the first memory area belongs to the specific external address space, converts, based on conversion information indicating correspondence relationship between the specific external address space and a specific internal address space which represents a specific address space in the first memory device, the first address information into second address information indicating a second memory area belonging to the specific internal address space.
    Type: Application
    Filed: October 26, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yohei HASEGAWA, Yoshiki SAITO, Shigehiro ASANO
  • Patent number: 9444604
    Abstract: A communication system includes a data sending terminal which sends data and a data receiving terminal which sends an acknowledgement, which indicates that the data is received, to the data sending terminal in reply to receiving the data, and the data receiving terminal includes a unit which judges whether it is necessary to resend the acknowledgement on the basis of judgment whether the data receiving terminal receives new data from the data sending terminal within a predetermined time since sending the acknowledgement.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: September 13, 2016
    Assignee: NEC CORPORATION
    Inventors: Yohei Hasegawa, Masahiro Jibiki
  • Publication number: 20160241465
    Abstract: A communications control device that, if a communications failure occurs at location in a first path for communications that extends across a plurality of communications layers, selects any second path from a candidate group including at least one second path for continuing communications without going via the location where the communications failure has occurred, on the basis of the time required for each second path to switch from the first path to the second path, and sends, to a communications device for performing the switching, an instruction for switching the first path to the selected second path and continuing communications.
    Type: Application
    Filed: April 25, 2014
    Publication date: August 18, 2016
    Applicant: NEC Corporation
    Inventors: Yohei HASEGAWA, Atsushi IWATA
  • Patent number: 9362637
    Abstract: To provide an electrical connector for circuit boards having lock fittings designed to reliably prevent damage to lock portions and inadvertent removal of mating connectors. The lock fittings have lock plate portions that extend along the inner surface of the lateral walls of the housing and are retained in place on said lateral walls, or which extend along the inner surface of the end walls and are retained in place on said end walls; upright face-reinforcing plate portions that extend along the upright faces of the protruding wall of the housing facing said lock plate portions and are retained in place on said protruding wall; and connecting bottom portions that extend along the bottom wall and connect the bottom wall-adjacent end portions of the lock plate portions and the upright face-reinforcing plate portions.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: June 7, 2016
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventor: Yohei Hasegawa
  • Publication number: 20160085517
    Abstract: A program information generating system includes an acquisition unit, a generating unit, and display control unit. The acquiring unit acquires program information which represents structure of a computer program and operation information which represents structure of operations. The generating unit generates first display information for generating a first display image which visually represents the structure of the computer program and second display information for generating a second display image which visually represents the structure of the operations. The program information includes section information which identifies a position of sections included in the computer program. The operation information includes section identification information which identifies the section corresponding to the operations.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 24, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yohei HASEGAWA, Akira KURODA, Hidenori MATSUZAKI, Nobuaki TOJO, Mayuko KOEZUKA
  • Publication number: 20160070471
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Application
    Filed: February 12, 2015
    Publication date: March 10, 2016
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • Publication number: 20160062871
    Abstract: A program information generating system includes an acquisition unit that acquires dependency information indicating dependency among a plurality of events generated by execution of a program and selection information identifying a selected event that is the event selected by a user; a generation unit that generates display information, on the basis of the dependency information and the selection information, such that a dependency path that is formed of the plurality of events having the dependency and includes the selected event is displayed in a distinguishable manner; and a display control unit that controls a display unit, on the basis of the display information, such that a display image indicating an execution state of the program is displayed.
    Type: Application
    Filed: May 21, 2015
    Publication date: March 3, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akira KURODA, Yohei Hasegawa, Hidenori Matsuzaki, Nobuaki Tojo, Mayuko Koezuka