Patents by Inventor Yoichi Asano

Yoichi Asano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5965802
    Abstract: An NO.sub.x sensor is produced by sintering a plurality of columnar crystals of .beta.-type Nb.sub.2 O.sub.5. The average value M of aspect ratios b/a (wherein a represents a width and b represents a length) in the columnar crystals is set in a range of 2.11<M.ltoreq.5. The NO.sub.x sensor has a high sensitivity to NO.sub.x via an enhancement attained by control of crystal type and structure.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: October 12, 1999
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Masaaki Nanaumi, Hiroshi Takeshita, Norihiro Ohta, Noriko Ohta, Yoshikazu Fujisawa, Yoichi Asano, Yoshiaki Takagi
  • Patent number: 5682545
    Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 28, 1997
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System Ltd.
    Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
  • Patent number: 5513082
    Abstract: This invention provides a small lamp socket device for a panel/printed board which can be fitted from the surface of a printed board with a one-touch operation. Contact portions for a pattern face and snap portions for clamping and contacting a panel/printed board are disposed at upper and lower positions of the walls of an insulating socket main body 1, to which a small lamp is fitted, so that they protrude and oppose one another with a predetermined space between them. The snap portions have resilience so that they can come into and out from the socket main body, and the panel/printed board is clamped by the contact portions 6 and the snap portions after passing through a fitting hole of the panel/printed board.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: April 30, 1996
    Assignee: Oshino Electric Lamp Works, Ltd.
    Inventor: Yoichi Asano
  • Patent number: 4044344
    Abstract: In a MIS dynamic memory, information is written in the memory cell at a predetermined address, the access to other plural addresses is made for a fixed time period under such a condition that the memory cell of the predetermined address is not refreshed, and the stored information is thereafter read out of the memory cell of the predetermined address. The level of the read information is compared with a predetermined threshold value, thereby determining the information hold time of the memory cell.
    Type: Grant
    Filed: May 12, 1976
    Date of Patent: August 23, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Hidetsugu Wada, Yoichi Asano, Yoshikazu Suzumura
  • Patent number: 3962687
    Abstract: In a method of inspection of a semiconductor memory device, selection signals for selecting a memory cell to be tested and a designation signal for designating the address of a predetermined memory cell are compared, to produce a mask instruction signal when the address of the memory cell to be tested is coincident with the address of the predetermined memory cell, and the judgment of the test result of the predetermined memory cell is masked by the mask instruction signal. If the predetermined memory cell is one known to be inferior during the wiring check, it will be also defection during the test of any characteristic. Since such memory cells with inferior wiring are masked in characteristic tests, the analysis of defects is facilitated.
    Type: Grant
    Filed: October 15, 1974
    Date of Patent: June 8, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Yoshikazu Suzumura, Yoichi Asano