Patents by Inventor Yoichi Iizuka

Yoichi Iizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8717113
    Abstract: An oscillator and a semiconductor integrated circuit device with an internal oscillator capable of compensating the temperature characteristics even when there is a large parasitic capacitance too large to ignore directly between the output terminals of the oscillator. In an oscillator containing an inductance element L, and a capacitive element C, and an amplifier each coupled in parallel across a first and second terminal, the amplifier amplifies the resonance generated by the inductance element and capacitive element and issues an output from the first terminal and the second terminal, and in which a first resistance element with a larger resistance value than the parasitic resistance of the inductance element between the first terminal and the second terminal, is coupled in serial with the capacitive element between the first terminal and the second terminal.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: May 6, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichi Iizuka, Yasuo Ikeda, Satoshi Onishi
  • Publication number: 20140119142
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Masayasu KOMYO, Yoichi IIZUKA
  • Patent number: 8653851
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: February 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Publication number: 20140016401
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.
    Type: Application
    Filed: September 19, 2013
    Publication date: January 16, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Publication number: 20130343144
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.
    Type: Application
    Filed: August 29, 2013
    Publication date: December 26, 2013
    Inventors: Masayasu KOMYO, Yoichi IIZUKA
  • Patent number: 8558572
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: October 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Patent number: 8552758
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: October 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Publication number: 20120223769
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 6, 2012
    Inventors: Masayasu KOMYO, Yoichi IIzuka
  • Patent number: 8253436
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: August 28, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Publication number: 20120200364
    Abstract: An oscillator and a semiconductor integrated circuit device with an internal oscillator capable of compensating the temperature characteristics even when there is a large parasitic capacitance too large to ignore directly between the output terminals of the oscillator. In an oscillator containing an inductance element L, and a capacitive element C, and an amplifier each coupled in parallel across a first and second terminal, the amplifier amplifies the resonance generated by the inductance element and capacitive element and issues an output from the first terminal and the second terminal, and in which a first resistance element with a larger resistance value than the parasitic resistance of the inductance element between the first terminal and the second terminal, is coupled in serial with the capacitive element between the first terminal and the second terminal.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 9, 2012
    Inventors: Yoichi Iizuka, Yasuo Ikeda, Satoshi Inishi
  • Publication number: 20120026812
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.
    Type: Application
    Filed: October 12, 2011
    Publication date: February 2, 2012
    Inventors: Masayasu KOMYO, Yoichi Iizuka
  • Patent number: 8102186
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: January 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Publication number: 20110255354
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Inventors: Masayasu KOMYO, Yoichi IIZUKA
  • Patent number: 7999572
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Patent number: 7956638
    Abstract: An impedance adjusting circuit that includes an external terminal to which an external resistor is connected, a first transistor array of a first conductivity type that is connected in parallel between the external terminal and a first power supply terminal and changes a voltage of the external terminal by adjusting an impedance in response to a first control signal, a second transistor array of a second conductivity type that is connected in parallel between the external terminal and a second power supply terminal and changes the voltage of the external terminal by adjusting the impedance in response to a second control signal, and a control circuit that specifies the first control signal according to a comparison result between the voltage of the external terminal and a reference voltage and specifies the second control signal in a different period from a period to specify the first control signal.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichi Iizuka, Masayasu Komyo
  • Publication number: 20110057720
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.
    Type: Application
    Filed: September 7, 2010
    Publication date: March 10, 2011
    Inventors: Masayasu KOMYO, Yoichi IIZUKA
  • Publication number: 20110057722
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.
    Type: Application
    Filed: September 7, 2010
    Publication date: March 10, 2011
    Inventors: Masayasu KOMYO, Yoichi Iizuka
  • Publication number: 20110057721
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.
    Type: Application
    Filed: September 7, 2010
    Publication date: March 10, 2011
    Inventors: Masayasu KOMYO, Yoichi IIZUKA
  • Publication number: 20100188116
    Abstract: An impedance adjusting circuit that includes an external terminal to which an external resistor is connected, a first transistor array of a first conductivity type that is connected in parallel between the external terminal and a first power supply terminal and changes a voltage of the external terminal by adjusting an impedance in response to a first control signal, a second transistor array of a second conductivity type that is connected in parallel between the external terminal and a second power supply terminal and changes the voltage of the external terminal by adjusting the impedance in response to a second control signal, and a control circuit that specifies the first control signal according to a comparison result between the voltage of the external terminal and a reference voltage and specifies the second control signal in a different period from a period to specify the first control signal.
    Type: Application
    Filed: January 4, 2010
    Publication date: July 29, 2010
    Inventors: Yoichi IIZUKA, Masayasu Komyo
  • Patent number: 7586955
    Abstract: A circuit that enables a loop-back test by adjusting phases of data and strobe signals at the input and output in an interface wherein the phase relationships between the data and the strobe signal for sampling the data are different between the input and output. In order to test a phase shift circuit 30 and a sampling circuit 40 on the input side, DQ and DQS are outputted with their phases aligned by a phase shift circuit 20 on the output side, DQ and DQS having the same phase are fed to input buffers 16 and 17, respectively, from output buffers 14 and 15, the phase of DQS is shifted by 90 degrees by phase shift circuit 30, and DQ is sampled by sampling circuit 40.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: September 8, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Yoichi Iizuka