Patents by Inventor Yoichi Iizuka

Yoichi Iizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7567880
    Abstract: An interface circuit includes a variable delay circuit and a delay adjustment circuit to automatically detect a data valid window of a DQ signal and adjust an optimum delay amount of a DQS signal, and a fixed delay circuit to delay the DQ signal by a delay amount tFIXDLY satisfying tFIXDLY>tMINDLY+tSKEW?tSETUP where a minimum delay amount in the variable delay circuit is tMINDLY, a skew between the DQ signal and the DQS signal is tSKEW, and a setup time of the DQ signal is tSETUP.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: July 28, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Yoichi Iizuka
  • Patent number: 7345602
    Abstract: Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data into first serial data, and the second parallel-to-serial converter converts the parallel data into second serial data. The mixing circuit receives the first serial data from the first parallel-to-serial converter and the second serial data from the second parallel-to-serial converter to output a signal emphasizing a change point of the first serial data. The clock generating circuit outputs a first set of clocks made up of clocks having mutually different phases and a second set of clocks made up of clocks having mutually different phases to the first and second parallel-to-serial converters, respectively. The first phase clock of the second set of clocks corresponds to the second phase clock of the first set of clocks.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: March 18, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Takanori Saeki, Yasushi Aoki, Tadashi Iwasaki, Toshihiro Narisawa, Makoto Tanaka, Yoichi Iizuka, Nobuhiro Ooki
  • Publication number: 20080048747
    Abstract: An interface circuit includes a variable delay circuit and a delay adjustment circuit to automatically detect a data valid window of a DQ signal and adjust an optimum delay amount of a DQS signal, and a fixed delay circuit to delay the DQ signal by a delay amount tFIXDLY satisfying tFIXDLY>tMINDLY+tSKEW?tSETUP where a minimum delay amount in the variable delay circuit is tMINDLY, a skew between the DQ signal and the DQS signal is tSKEW, and a setup time of the DQ signal is tSETUP.
    Type: Application
    Filed: July 20, 2007
    Publication date: February 28, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yoichi Iizuka
  • Publication number: 20070047337
    Abstract: A circuit that enables a loop-back test by adjusting phases of data and strobe signals at the input and output in an interface wherein the phase relationships between the data and the strobe signal for sampling the data are different between the input and output. In order to test a phase shift circuit 30 and a sampling circuit 40 on the input side, DQ and DQS are outputted with their phases aligned by a phase shift circuit 20 on the output side, DQ and DQS having the same phase are fed to input buffers 16 and 17, respectively, from output buffers 14 and 15, the phase of DQS is shifted by 90 degrees by phase shift circuit 30, and DQ is sampled by sampling circuit 40.
    Type: Application
    Filed: July 28, 2006
    Publication date: March 1, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Yoichi Iizuka
  • Publication number: 20070024476
    Abstract: Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data into first serial data, and the second parallel-to-serial converter converts the parallel data into second serial data. The mixing circuit receives the first serial data from the first parallel-to-serial converter and the second serial data from the second parallel-to-serial converter to output a signal emphasizing a change point of the first serial data. The clock generating circuit outputs a first set of clocks made up of clocks having mutually different phases and a second set of clocks made up of clocks having mutually different phases to the first and second parallel-to-serial converters, respectively. The first phase clock of the second set of clocks corresponds to the second phase clock of the first set of clocks.
    Type: Application
    Filed: July 27, 2006
    Publication date: February 1, 2007
    Inventors: Takanori Saeki, Yasushi Aoki, Tadashi Iwasaki, Toshihiro Narisawa, Makoto Tanaka, Yoichi Iizuka, Nobuhiro Ooki
  • Patent number: 6489808
    Abstract: A buffer circuit has a high-impedance function mode. The buffer circuit is for outputting a buffer output level. The buffer circuit comprises a buffer output control section for controlling the buffer output level to an opposite level in a moment before the buffer circuit becomes the high-impedance function mode. The opposite level is a level opposite to a present buffer output level.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: December 3, 2002
    Assignee: NEC Corporation
    Inventor: Yoichi Iizuka
  • Publication number: 20020145445
    Abstract: A buffer circuit has a high-impedance function mode. The buffer circuit is for outputting a buffer output level. The buffer circuit comprises a buffer output control section for controlling the buffer output level to an opposite level in a moment before the buffer circuit becomes the high-impedance function mode. The opposite level is a level opposite to a present buffer output level.
    Type: Application
    Filed: May 29, 2002
    Publication date: October 10, 2002
    Inventor: Yoichi Iizuka
  • Patent number: 6006348
    Abstract: A flip flop circuit for a scan test comprises a first latch circuit for latching and outputting data signal D in synchronization with control signal CLK when control signal SC1 is set at one level and latching and outputting scan in data signal SIN in synchronization with control signal SC1 when control signal CLK is set at the other level, and a second latch circuit for latching and outputting an output of the first latch circuit in synchronization with control signal CLK when control signal SC2 is set at one level and latching and outputting an output of the first latch circuit in synchronization with control signal SC2 when control signal CLK is set at the other level. In this way, the area of the circuit is decreased by commonly using one latch circuit for a data signal and a scan in data signal. Also, the skew adjustment is not required during a scan test by operating with two-phase clocks during both scan shift operation and scan normal operation.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: December 21, 1999
    Assignee: NEC Corporation
    Inventors: Mikiko Sode, Yoichi Iizuka