Abstract: A stainless steel pipe of the bright annealing finish type, having a highly-soothed inner surface according to the present invention is characterized in that the inner surface roughness of the pipe, expressed in Rmax is 1.0 micrometer or less, and suitable as a clean pipe for use in an apparatus for the production of semiconductors. According to the method of production of the present invention, a stainless steel pipe having a highly-smoothed inner surface can be obtained by cold drawing and bright annealing treatment only. By this method, such a treatment that has been considered to be essential, for example, electrochemical polishing can be omitted, so that the production cost can be greatly reduced. The stainless steel pipe of the invention can thus be widely utilized in the fields of the production of semiconductors and the like.

Abstract: A matrix-type display control device suited to large capacity displays while achieving low power consumption operation is achieved by improving the display data transfer method. The module controller 100 of a simple matrix-type liquid crystal display comprises a low frequency oscillator 110, timing signal generator 120, standby circuit (display data refresh detection circuit) 130, high frequency oscillator 140, and a direct memory access (DMA circuit) 150. This low frequency oscillator 110 constantly generates the low frequency clock f.sub.L. Timing signal generator 120 generates the scan start signal YD required for the LCD module 200, and other signals based on the low frequency clock f.sub.L. Standby circuit 130 generates the intermittent operation start control signal ST when the display data in VRAM 12 is updated as determined by monitoring the system bus 14a for communications with host MPU 10. The high frequency oscillator 140 generates the high frequency clock f.sub.

Abstract: A matrix display apparatus is provided for displaying an image in accordance with display data. The display matrix comprises a plurality of scanning electrodes and a plurality of signal electrodes arranged in a matrix. A first driving circuit applies a plurality of selection voltages to the scanning electrodes. The scanning electrodes are divided into groups of h scanning electrodes. A selection voltage is applied to each of the plurality of scanning electrodes selected from the plurality of selection voltages in accordance with the selection pattern data. The second driving circuit provides a plurality of signal voltages to the plurality of signal electrodes. The second driver circuit comprises a memory for storing the display data for at least one group of h scanning electrodes and a selecting circuit for selecting a signal voltage applied to each of the plurality of signal electrodes.

Abstract: An oscillation device and a display data processing device adjust variables such as the duty ratio of the oscillation frequency, and control autonomously timings between components such as memories. First and second switching devices disposed within charging and discharging devices are turned on and off by an output of a MOS buffer, enabling adjustment of the frequency and duty ratio of an oscillation signal. Equivalent circuits are provided corresponding to display data RAM, CGROM, and address decoders, data is read sequentially from the display data RAM and the CGROM when an EIRAM signal is enabled, and a DLAT signal is stored in a driver circuit. The equivalent circuits enable each of EIROM, EILAT, and RS signals at points when the read data is confirmed or thereafter. When the RS signal is enabled, EIRAM and other signals are sequentially disabled and the display data RAM and other components switch to a precharge operation.

Abstract: A matrix-type display control device suited to large capacity displays while achieving low power consumption operation is achieved by improving the display data transfer method. The module controller 100 of a simple matrix-type liquid crystal display comprises a low frequency oscillator 110, timing signal generator 120, standby circuit (display data refresh detection circuit) 130, high frequency oscillator 140, and a direct memory access (DMA circuit) 150. This low frequency oscillator 110 constantly generates the low frequency clock f.sub.L. Timing signal generator 120 generates the scan start signal YD required for the LCD module 200, and other signals based on the low frequency clock f.sub.L. Standby circuit 130 generates the intermittent operation start control signal ST when the display data in VRAM 12 is updated as determined by monitoring the system bus 14a for communications with host MPU 10. The high frequency oscillator 140 generates the high frequency clock f.sub.

Abstract: A rolling bearing is composed of an outer race having an inner-race raceway on an outer peripheral wall thereof, an outer race having an outer-race raceway on an inner peripheral wall thereof, a plurality of rolling elements interposed for rotation between the outer-race raceway and the inner race, and a lubricant composition filled in a space, which is defined between the inner-race raceway and the outer-race raceway, at a position where the plurality of rolling elements are disposed. The rolling bearing features: (a) at least one of the inner-race and outer-race raceways is made of steel having an oxygen content not higher than 6 ppm; (b) at least a raceway surface of said at least one raceway has been hardened by heat treatment; (c) the lubricant composition comprises as a base oil a synthetic lubricant having a kinematic viscosity of 60-160 cSt at 40.degree. C.; and (d) the lubricant composition further comprises 18-28 wt. % of a thickener which comprises a polyurea compound.

Abstract: A rolling bearing is composed of an outer race, an inner race and rolling elements interposed between the outer race and the inner race. A lubricant composition comprising a polyether lubricant as a base oil is filled in the bearing. Preferably, the polyether lubricant has a kinematic viscosity 90-160 cSt at 40.degree. C.

Abstract: A method and circuit for activating a liquid crystal matrix display panel in which during each selecting period, each liquid crystal cell pixel of the matrix, whether selected or unselected, receives either a primary selecting signal voltage or non-selecting signal voltage as well as an additional different secondary voltage to generate substantially homogeneous crosstalk noise over the entire display. The signal voltage applied to a pixel during a selecting period can vary between a primary selecting or non-selecting voltage applied for a first time interval followed by or preceded by a secondary voltage intermediate the selecting and non-selecting voltage applied for a second interval. Alternatively, the primary signal voltage applied to the pixel for a first time interval can be a selecting or non-selecting voltage and secondary voltage applied for a second time interval can be the other.

Abstract: A variable capacitance circuit comprising a capacitor array, associated switching elements and transient impedance varying circuits. The capacitor array comprises a plurality of capacitor elements connected to a common node coupled to a crystal oscillator in a crystal oscillator portion and each capacitor element includes a connected switching element that controls activation of selected capacitor elements that are selectively placed in operation as load capacitance with the crystal oscillator to change and adjust its frequency. Further, circuits are provided in a temperature compensation portion to selectively control the activation of the switching elements based upon decoded compensating values provided in memory, such as based upon sensed oscillator temperature conditions.

Abstract: Generally speaking, in accordance with the invention, a semiconductor memory device comprises a static RAM cell having a serial-parallel data conversion function, formed of seven transistors. The RAM can read/write and includes bit lines exclusively for reading and bit lines which are exclusively for writing the data. Data is read through the bit lines for exclusive reading by means of a single gate transistor. The semiconductor memory device provides a memory whose area is small in spite of including therein a serial-parallel conversion function. Further, access to the memory cell is freely available from the system side.

Abstract: An oscillator circuit wherein the impedance at the output terminal can be selectively decreased for a short period of time to thereby increase the closed loop gain is provided. The oscillator circuit includes a quartz crystal vibrator and a C-MOS inverter having a drain output terminal for producing a high frequency signal thereat, the gate output terminal being fed back through the quartz crystal vibrator to a gate input terminal to define a predetermined closed loop gain. The invention is particularly characterized by a control circuit external to the oscillator circuit that is adapted to produce a control signal for a predetermined period of time.

Abstract: An electronic timepiece having circuitry for automatically adjusting the time rate by comparing same to a randomly selected reference, is provided. A timing rate circuit includes an oscillator for producing a high frequency time standard signal and a divider for producing a low frequency timekeeping signal. The divider includes a plurality of series-connected divider stages, each divider stage being adapted to produce an intermediate frequency signal. A counter is provided for receiving the low frequency timekeeping signal and producing an elapsed time signal representative of time counted thereby. The instant invention is particularly characterized by an error counter coupled to one of the divider stages for receiving an intermediate frequency signal produced thereby for a randomly selected reference period.

Abstract: A semiconductor integrated power-on reset circuit that is formed on the same monolithic substrate as the circuitry that same is adapted to reset in order to obtain higher component density on the monolithic substrate is provided. The circuitry on the monolithic substrate defines a predetermined parasitic capacitance and includes a voltage supply for selectively applying a supply voltage to the circuitry to operate the circuitry at the supply voltage after a first predetermined interval of time. The power-on reset circuit is disposed intermediate the voltage supply and the circuitry and includes at least one pair of complementary coupled P-channel and N-channel MOS transistors, coupled to define an output terminal having the predetermined parasitic capacitance thereat.