Abstract: Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

Abstract: A structure having trench isolation which protects a nitride liner in the trench during subsequent plasma processing. The structure includes a trench formed in a semiconductor substrate, the trench having sidewalls and a bottom. A thermal oxide layer is formed on the bottom and sidewalls of the trench so as to remove substrate damage caused during etching of the semiconductor substrate to form the trench. A material layer is formed on the thermal oxide layer so as to prevent the bottom and sidewalls of the trench from being oxidized. Then, a protection layer is formed on the oxidation barrier layer. The trench is filled with a trench fill material uniformly with respect to the bottom and sidewalls of the trench.

Abstract: Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on the integrated circuit substrate that extends over an edge of the trench and along an upper portion of a first sidewall of the trench. An insulating material is positioned adjacent the silicon layer that extends across some, or all, of the trench to define the isolation region. Methods of forming such integrated circuit devices are also provided.

Abstract: Methods of forming a cell pad contact hole on an integrated circuit include forming adjacent gates on an integrated circuit substrate having a source/drain region extending between the gates. Gate spacers are formed on facing sidewalls of the adjacent gates. A cell pad contact hole is formed aligned to the gates and gate spacers that exposes the source/drain region in the integrated circuit substrate. A first poly film is formed in the cell pad contact hole. An ion region is formed in the source/drain region by ion-implanting through the first poly film and a second poly film is formed on the first poly film that substantially fills the cell pad contact hole.

Abstract: An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.

Abstract: An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.

Abstract: Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on the integrated circuit substrate that extends over an edge of the trench and along an upper portion of a first sidewall of the trench. An insulating material is positioned adjacent the silicon layer that extends across some, or all, of the trench to define the isolation region. Methods of forming such integrated circuit devices are also provided.

Abstract: A semiconductor device having a shallow trench isolation (STI) structure, which reduces leakage current between adjacent P-FETs, and a manufacturing method thereof. The device comprises a semiconductor substrate having first and second trenches, the first trench being formed in a cell area; a first sidewall oxide layer formed on inner surfaces of the first and second trenches; a second sidewall oxide layer formed on a surface of the first sidewall oxide layer in the second trench; a first relief liner formed on the first sidewall oxide layer in the first trench; a second relief liner formed on the first relief liner in the first trench, and also formed on the second sidewall oxide layer in the second trench; and a dielectric material formed within the first and second trenches.

Abstract: A gate having sidewalls is formed on an integrated circuit substrate. A barrier layer spacer is formed on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is formed on the portion of the barrier layer spacer protruding from the sidewalls of the gate. Related devices are also provided.

Abstract: An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.

Abstract: Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.

Abstract: Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on the integrated circuit substrate that extends over an edge of the trench and along an upper portion of a first sidewall of the trench. An insulating material is positioned adjacent the silicon layer that extends across some, or all, of the trench to define the isolation region. Methods of forming such integrated circuit devices are also provided.

Abstract: A semiconductor device including a cylinder-type capacitor and a manufacturing method thereof are provided. The semiconductor device includes dielectric layer patterns formed on a semiconductor substrate. The dielectric layer patterns extend to the same height in a cell region and a peripheral circuit region of the semiconductor substrate and define a hole in the cell region. A lower electrode of a cylinder-type capacitor is formed to contact the bottom of the hole with a predetermined gap between the outer wall of the lower electrode and the sidewall of the hole. A dielectric layer is formed on the dielectric layer patterns and the lower electrode on the cell region. An upper electrode is formed on the dielectric layer. According to the semiconductor device and the manufacturing method thereof, a cylinder-type capacitor is formed in the cell region without generating a step difference between the cell region and the peripheral circuit region.

Abstract: A semiconductor device including a cylinder-type capacitor and a manufacturing method thereof are provided. The semiconductor device includes dielectric layer patterns formed on a semiconductor substrate. The dielectric layer patterns extend to the same height in a cell region and a peripheral circuit region of the semiconductor substrate and define a hole in the cell region. A lower electrode of a cylinder-type capacitor is formed to contact the bottom of the hole with a predetermined gap between the outer wall of the lower electrode and the sidewall of the hole. A dielectric layer is formed on the dielectric layer patterns and the lower electrode on the cell region. An upper electrode is formed on the dielectric layer. According to the semiconductor device and the manufacturing method thereof, a cylinder-type capacitor is formed in the cell region without generating a step difference between the cell region and the peripheral circuit region.

Abstract: A method and structure of forming an trench isolation is provided which protects a nitride liner in the trench during subsequent plasma processing by forming a high temperature oxide layer, such as an HTO oxide layer or LP-TEOS oxide layer. The method includes the steps of forming a trench mask on a semiconductor substrate to define a trench forming region, etching the semiconductor substrate using the trench mask and forming a trench therein, forming a thermal oxide layer on a bottom and sidewalls of the trench so as to remove substrate damage caused by the step of etching the semiconductor substrate, forming a material layer on the thermal oxide layer so as to prevent the bottom and sidewalls of the trench from being oxidized, forming a protection layer on the oxidation barrier layer, plasma processing the bottom and sidewalls of the trench, and filling up the trench with a trench fill material uniformly with respect to the bottom and sidewalls of the trench.

Abstract: An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.

Abstract: A semiconductor device having a shallow trench isolation (STI) structure, which reduces leakage current between adjacent P-FETs, and a manufacturing method thereof. The device comprises a semiconductor substrate having first and second trenches, the first trench being formed in a cell area; a first sidewall oxide layer formed on inner surfaces of the first and second trenches; a second sidewall oxide layer formed on a surface of the first sidewall oxide layer in the second trench; a first relief liner formed on the first sidewall oxide layer in the first trench; a second relief liner formed on the first relief liner in the first trench, and also formed on the second sidewall oxide layer in the second trench; and a dielectric material formed within the first and second trenches.

Abstract: A method of forming an isolation trench in a semiconductor substrate includes the steps of sequentially depositing first and second insulating layers over the substrate, subsequently etching the second and first insulating layers to define active and non-active regions according to a patterned masking photoresist layer, excessively etching a part of the thickness of the substrate, removing parts of the first insulating layer by undercutting the sides of the non-active region so as to expose parts of the substrate in the active region, etching the substrate by using the second insulating layer as a trench patterned masking layer to form a trench in which the edges of the exposed parts of the substrate are rounded, depositing a third insulating layer on the bottom and side walls of the trench and the rounded parts of the substrate to repair the parts of the substrate damaged when forming the trench, depositing a fourth insulating layer over the second insulating layer so as to completely fill the trench, etchin

Abstract: Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.

Abstract: A method of forming trench isolation which protects a nitride liner in the trench during subsequent plasma processing, by forming a high temperature oxide layer, such as an HTO oxide layer or LP-TEOS oxide layer. A trench mask is formed on a semiconductor substrate to define a trench forming region, the semiconductor substrate is etched using the trench mask to form a trench, a thermal oxide layer is formed on a bottom and sidewalls of the trench to remove substrate damage caused by the etching, a material layer is formed on the thermal oxide layer to prevent the bottom and sidewalls of the trench from being oxidized, a protection layer is formed on the oxidation barrier layer, the bottom and sidewalls of the trench are plasma processed, and the trench is then filled with a trench fill material uniformly with respect to the bottom and sidewalls.