Patents by Inventor Yong-Suk Choi
Yong-Suk Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20060128098Abstract: A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer.Type: ApplicationFiled: February 7, 2006Publication date: June 15, 2006Inventors: Heeseog Jeon, Seung-beom Yoon, Yong-tae Kim, Yong-suk Choi
-
Patent number: 7037781Abstract: Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.Type: GrantFiled: July 9, 2004Date of Patent: May 2, 2006Assignee: Samsung Electronics, Co., Ltd.Inventors: Yong-suk Choi, Seung-beom Yoon, Seong-gyun Kim
-
Patent number: 7029974Abstract: A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer.Type: GrantFiled: March 17, 2005Date of Patent: April 18, 2006Assignee: Samsung Electronics, Co., Ltd.Inventors: Heeseog Jeon, Seung-beom Yoon, Yong-tae Kim, Yong-suk Choi
-
Publication number: 20060079054Abstract: A non-volatile memory device includes a control gate electrode disposed on a substrate with a first insulation layer interposed therebetween and a floating gate disposed in a hole exposing substrate through the control gate electrode and the first insulation layer. A second insulation layer is interposed between the floating gate and the substrate, and between the floating gate and the control gate.Type: ApplicationFiled: October 7, 2005Publication date: April 13, 2006Inventors: Yong-Suk Choi, Seung-Beom Yoon, Yong-Tae Kim, Jin-Woo Kim
-
Publication number: 20060043332Abstract: An etchant for removing an indium oxide layer includes sulfuric acid as a main oxidizer, an auxiliary oxidizer such as H3PO4, HNO3, CH3COOH, HClO4, H2O2, and a Compound A that is obtained by mixing potassium peroxymonosulfate (2KHSO5), potassium bisulfate (KHSO4), and potassium sulfate (K2SO4) together in the ratio of 5:3:2, an etching inhibitor comprising an ammonium-based material, and water. The etchant may remove desired portions of the indium oxide layer without damage to a photoresist pattern or layers underlying the indium oxide layer.Type: ApplicationFiled: August 23, 2005Publication date: March 2, 2006Inventors: Hong-Je Cho, Seung-Yong Lee, Joon-Woo Lee, Jae-Yeon Lee, Seung-Hwan Chon, Yong-Suk Choi, Young-Chul Park, Jin-Su Kim, Kyu-Sang Kim, Dong-Uk Choi, Kwan-Tack Lim
-
Publication number: 20060008100Abstract: Disclosed herein is an apparatus for producing 3D sound. The apparatus includes a determination unit, a mono sound spreading unit, a stereo sound spreading unit, a selection unit, and a 3D sound accelerator. The determination unit receives a source sound file and determines whether the source sound file is mono or stereo. The mono sound spreading unit converts the source sound into pseudo-stereo sound and performs sound spreading on the pseudo-stereo sound, if the source sound is determined to be mono. The stereo sound spreading unit performs sound spreading on the source sound, if the source sound is determined to be stereo. The selection unit receives the output of the mono sound spreading unit or stereo sound spreading unit, and transfers the output to headphones if the headphone reproduction has been selected.Type: ApplicationFiled: July 7, 2005Publication date: January 12, 2006Inventors: Poong-Min Kim, Hyun-Suk Kim, Jin-Wook Kim, Dong-Woo Lee, In-Ho Lee, Yong-Suk Choi, Jeong-Mo Koo, Myung-Cheol Lee, Dong-Sun Shin, Jong-Woo Kim
-
Publication number: 20050208744Abstract: A split gate type nonvolatile semiconductor memory device and a method of fabricating a split gate type nonvolatile semiconductor memory device are provided. A gate insulating layer and a floating-gate conductive layer are formed on a semiconductor substrate. A mask layer pattern is formed on the floating-gate conductive layer to define a first opening extending in a first direction. First sacrificial spacers having a predetermined width are formed on both sidewalls corresponding to the mask layer pattern. An inter-gate insulating layer is formed on the floating-gate conductive layer. The first sacrificial spacers are removed, and the floating-gate conductive layer is etched until the gate insulating layer is exposed. A tunneling insulating layer is formed on an exposed portion of the floating-gate conductive layer. A control-gate conductive layer is formed on a surface of the semiconductor substrate. Second sacrificial spacers having predetermined widths are formed on the control-gate conductive layer.Type: ApplicationFiled: March 17, 2005Publication date: September 22, 2005Inventors: Heeseog Jeon, Seung-beom Yoon, Yong-tae Kim, Yong-suk Choi
-
Publication number: 20050153502Abstract: A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate.Type: ApplicationFiled: December 29, 2004Publication date: July 14, 2005Inventors: Jae-Hwang Kim, Yong-Suk Choi, Seung-Beom Yoon, Yong-Tae Kim, Young-Sam Park
-
Publication number: 20050106816Abstract: A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.Type: ApplicationFiled: November 12, 2004Publication date: May 19, 2005Inventors: Yong-suk Choi, Seung-beom Yoon, Seong-gyun Kim, Jae-Hwang Kim
-
Publication number: 20050101080Abstract: A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection gate electrode and spaced apart from the selection gate electrode. The non-volatile memory device further comprises a tunnel insulating layer intervening between the active region and each of the selection gate electrode and the floating gate electrode, a separation insulating pattern intervening between the selection gate electrode and the floating gate electrode, an erasing gate electrode disposed over the floating gate electrode and crossing over the active region parallel to the selection gate electrode, and an erasing gate insulating layer intervening between the erasing gate electrode and the floating gate electrode. The selection gate electrode is formed without a photoresist pattern.Type: ApplicationFiled: December 15, 2004Publication date: May 12, 2005Inventors: Yong-Suk Choi, Og-Hyun Lee
-
Patent number: 6878987Abstract: A split gate memory device and fabricating method thereof, wherein gate insulating and polysilicon layers are sequentially formed on a substrate. The polysilicon layer is patterned and a capping insulating layer is formed on portions thereof. A pair of self-aligned control gates having identical bottom widths are formed with a tunnel insulating layer interposed between the control gates and sidewalls of the polysilicon layer pattern and capping insulating layer. The tunnel insulating layer, patterned polysilicon layer and gate insulating layer are selectively etched to expose a portion of the substrate thereby forming a pair of floating gates. Ions are implanted into the exposed substrate and portions of the substrate adjoining the control gates to form a common source region and a drain region, respectively. The capping insulating layer on the floating gate protects an acute section of the tunnel insulating layer from attack during the etching and ion implantation.Type: GrantFiled: May 6, 2003Date of Patent: April 12, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Og-Hyun Lee, Yong Suk Choi
-
Publication number: 20050054167Abstract: Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.Type: ApplicationFiled: July 9, 2004Publication date: March 10, 2005Inventors: Yong-suk Choi, Seung-beom Yoon, Seong-gyun Kim
-
Publication number: 20050051836Abstract: Embodiments of the invention include a gate insulating layer formed on a semiconductor substrate; a spacer-type floating gate and a spacer-type dummy pattern, which are formed on the gate insulating layer and separated apart from each other, the floating gate and the dummy pattern having round surfaces that face outward; a pair of insulating spacers, which are formed on a sidewall of the floating gate and a sidewall of the dummy pattern which face each other; a control gate formed in a self-aligned manner between the pair of insulating spacers; a tunnel insulating layer interposed between the floating gate and the control gate; and source and drain regions formed in the semiconductor substrate outside the floating gate and the dummy pattern.Type: ApplicationFiled: August 11, 2004Publication date: March 10, 2005Inventors: Yong-Suk Choi, Seung-Beom Yoon
-
Patent number: 6847078Abstract: A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection gate electrode and spaced apart from the selection gate electrode. The non-volatile memory device further comprises a tunnel insulating layer intervening between the active region and each of the selection gate electrode and the floating gate electrode, a separation insulating pattern intervening between the selection gate electrode and the floating gate electrode, an erasing gate electrode disposed over the floating gate electrode and crossing over the active region parallel to the selection gate electrode, and an erasing gate insulating layer intervening between the erasing gate electrode and the floating gate electrode. The selection gate electrode is formed without a photoresist pattern.Type: GrantFiled: June 10, 2003Date of Patent: January 25, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Suk Choi, Og-Hyun Lee
-
Publication number: 20040185628Abstract: In a method of forming a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory device, a plurality of first gates may be formed on a semiconductor substrate. A plurality of charge storage spacers may be formed on the plurality of first gates so that a given charge storage spacer may be disposed on a sidewall of a given first gate. A plurality of second gates may be disposed on the plurality of first gates so that a given second gate is on a sidewall of a given first gate and covers a given charge storage spacer.Type: ApplicationFiled: January 22, 2004Publication date: September 23, 2004Inventor: Yong-Suk Choi
-
Patent number: 6793789Abstract: Disclosed is a polymeric reference electrode membrane comprising (a) one selected from a porous polymer or a hydrophilic plasticizer; (b) a lipophilic polymer; and optionally an adhesion-enhancing material. A reference electrode equipped with the polymeric reference electrode membrane can be shortened the preconditioning time, and extended lifetime for storage and use owing to excellent adhesion, and showed reproducibility and good yield. So, a miniaturized multi-potentiometric sensor can be fabricated comprising a solid-state reference electrode of the present invention and a set of ion-selective electrodes, thus being useful in the potentiometric fields, including clinical, environmental, food and industrial analysis.Type: GrantFiled: September 22, 2001Date of Patent: September 21, 2004Assignee: Geun Sig ChaInventors: Yong Suk Choi, Sung Dong Lee, Seong Hee Oh, Hyo Lin Lee, Jae Ho Shin, Jeonghan Ha, Hakhyun Nam, Geun Sig Cha
-
Publication number: 20040118814Abstract: An etching solution for a multiple layer of copper and molybdenum includes: about 5% to about 30% by weight of a hydrogen peroxide; about 0.5% to about 5% by weight of an organic acid; about 0.2% to about 5% by weight of a phosphate; about 0.2% to about 5% by weight of a first additive having nitrogen; about 0.2% to about 5% by weight of a second additive having nitrogen; about 0.01% to about 1.0% by weight of a fluoric compound; and de-ionized water making a total amount of the etching solution 100% by weight.Type: ApplicationFiled: December 11, 2003Publication date: June 24, 2004Inventors: Seong-Su Kim, Yong-Suk Choi, Gee-Sung Chae, Gyoo-Chul Jo, Oh-Nam Kwon, Kyoung-Mook Lee, Yong-Sup Hwang, Seung-Yong Lee
-
Publication number: 20040046204Abstract: A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection gate electrode and spaced apart from the selection gate electrode. The non-volatile memory device further comprises a tunnel insulating layer intervening between the active region and each of the selection gate electrode and the floating gate electrode, a separation insulating pattern intervening between the selection gate electrode and the floating gate electrode, an erasing gate electrode disposed over the floating gate electrode and crossing over the active region parallel to the selection gate electrode, and an erasing gate insulating layer intervening between the erasing gate electrode and the floating gate electrode. The selection gate electrode is formed without a photoresist pattern.Type: ApplicationFiled: June 10, 2003Publication date: March 11, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Yong-Suk Choi, Og-Hyun Lee
-
Publication number: 20030214864Abstract: A split gate memory device and fabricating method thereof, wherein gate insulating and polysilicon layers are sequentially formed on a substrate. The polysilicon layer is patterned and a capping insulating layer is formed on portions thereof. A pair of self-aligned control gates having identical bottom widths are formed with a tunnel insulating layer interposed between the control gates and sidewalls of the polysilicon layer pattern and capping insulating layer. The tunnel insulating layer, patterned polysilicon layer and gate insulating layer are selectively etched to expose a portion of the substrate thereby forming a pair of floating gates. Ions are implanted into the exposed substrate and portions of the substrate adjoining the control gates to form a common source region and a drain region, respectively. The capping insulating layer on the floating gate protects an acute section of the tunnel insulating layer from attack during the etching and ion implantation.Type: ApplicationFiled: May 6, 2003Publication date: November 20, 2003Inventors: Og-Hyun Lee, Yong Suk Choi
-
Publication number: 20020065332Abstract: Disclosed is a polymeric reference electrode membrane comprising (a) one selected from a porous polymer or a hydrophilic plasticizer; (b) a lipophilic polymer; and optionally an adhesion-enhancing material. A reference electrode equipped with the polymeric reference electrode membrane can be shortened the preconditioning time, and extended lifetime for storage and use owing to excellent adhesion, and showed reproducibility and good yield. So, a miniaturized multi-potentiometric sensor can be fabricated comprising a solid-state reference electrode of the present invention and a set of ion-selective electrodes, thus being useful in the potentiometric fields, including clinical, environmental, food and industrial analysis.Type: ApplicationFiled: September 22, 2001Publication date: May 30, 2002Inventors: Yong Suk Choi, Sung Dong Lee, Seong Hee Oh, Hyo Lin Lee, Jae Ho Shin, Jeonghan Ha, Hakhyun Nam, Geun Sig Cha