Abstract: A scan driver has a plurality of stages configured to supply a scan signal to scan lines. The plurality of stages include a stage coupled to a scan line of the scan lines. The stage includes a first transistor including a gate electrode, a drain electrode and a source electrode and is configured to output the scan signal to the scan line; a second transistor provided on a side of the first transistor and connected to the drain electrode; a third transistor provided on the side of the first transistor and connected to the source electrode; a capacitor provided between the scan line and the first transistor; a first dummy transistor provided between the first transistor and the capacitor and connected to the capacitor; and a second dummy transistor provided between the first transistor and the second transistor and connected to both the first transistor and the second transistor.

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.

Abstract: A liquid crystal display device includes a display area, a peripheral area, and a boundary area between the display area and the peripheral area and further includes: a first substrate; a switching element disposed on the first substrate in the display area; a pad disposed on the first substrate in the peripheral area and electrically connected with the switching element; a protective film disposed on the first substrate in the display area, the peripheral area, and the boundary area, and covering the switching element and the pad; a color filter disposed on the protective film in the display area; and a planarization film covering the color filter and contacting the protective film in the boundary area and the peripheral area. The planarization film is provided with a first opening overlapping the pad and at least one second opening formed in the boundary area.

Abstract: An LCD includes: pixel electrodes; a common electrode including a plurality of slits; and a liquid crystal layer interposed between the pixel electrodes and the common electrode. The plurality of slits include a first slit and a second slit that are disposed adjacent to each other in a first direction. The first slit includes a first central portion and a first extension portion extending from the first central portion toward the second slit, and the second slit includes a second central portion and a first extension portion extending from the second central portion toward the first slit. An end of the first extension portion of the first slit and an end of the first extension portion of the second slit are spaced apart from each other; and disposed, in a staggered manner, on opposite sides of an imaginary center line connecting the first central portion and the second central portion.

Abstract: A scan driver has a plurality of stages configured to supply a scan signal to scan lines. The plurality of stages include a stage coupled to a scan line of the scan lines. The stage includes a first transistor including a gate electrode, a drain electrode and a source electrode and is configured to output the scan signal to the scan line; a second transistor provided on a side of the first transistor and connected to the drain electrode; a third transistor provided on the side of the first transistor and connected to the source electrode; a capacitor provided between the scan line and the first transistor; a first dummy transistor provided between the first transistor and the capacitor and connected to the capacitor; and a second dummy transistor provided between the first transistor and the second transistor and connected to both the first transistor and the second transistor.

Abstract: A liquid crystal display device includes a display area, a peripheral area, and a boundary area between the display area and the peripheral area and further includes: a first substrate; a switching element disposed on the first substrate in the display area; a pad disposed on the first substrate in the peripheral area and electrically connected with the switching element; a protective film disposed on the first substrate in the display area, the peripheral area, and the boundary area, and covering the switching element and the pad; a color filter disposed on the protective film in the display area; and a planarization film covering the color filter and contacting the protective film in the boundary area and the peripheral area. The planarization film is provided with a first opening overlapping the pad and at least one second opening formed in the boundary area.

Abstract: A display device includes a substrate, a gate line connected to a gate driver, a reference voltage line, a data line crossing the gate line and the reference voltage line, a first thin film transistor including a first drain electrode and connected to the gate line and the data line, a second thin film transistor including a second drain electrode, a third thin film transistor connected to the gate line, the reference voltage line, and the second thin film transistor, and a pixel electrode including a first sub-pixel electrode connected to the first thin film transistor and a second sub-pixel electrode connected to the second thin film transistor. The first drain electrode overlaps the reference voltage line, and an area of a region in which the first drain electrode and the reference voltage line overlap each other increases in a direction toward the gate driver.

Abstract: An LCD includes: pixel electrodes; a common electrode including a plurality of slits; and a liquid crystal layer interposed between the pixel electrodes and the common electrode. The plurality of slits include a first slit and a second slit that are disposed adjacent to each other in a first direction. The first slit includes a first central portion and a first extension portion extending from the first central portion toward the second slit, and the second slit includes a second central portion and a first extension portion extending from the second central portion toward the first slit. An end of the first extension portion of the first slit and an end of the first extension portion of the second slit are spaced apart from each other; and disposed, in a staggered manner, on opposite sides of an imaginary center line connecting the first central portion and the second central portion.

Abstract: A thin film transistor (TFT) substrate includes a base substrate, a TFT disposed on the base substrate. The TFT includes a gate electrode, a semiconductor layer comprising a channel region, and a source electrode and a drain electrode spaced apart from one another by a length of the channel region. The TFT substrate further includes a gate insulating layer disposed between the gate electrode and the semiconductor layer and a measuring pattern configured to measure a length of the channel region.

Abstract: A thin film transistor (TFT) substrate includes a base substrate, a TFT disposed on the base substrate. The TFT includes a gate electrode, a semiconductor layer comprising a channel region, and a source electrode and a drain electrode spaced apart from one another by a length of the channel region. The TFT substrate further includes a gate insulating layer disposed between the gate electrode and the semiconductor layer and a measuring pattern configured to measure a length of the channel region.

Abstract: A liquid crystal display device according to the present invention includes: a first substrate; a first color filter and a second color filter provided on the first substrate and including an overlapping portion where at least parts of the first and second color filters overlap each other; and a light blocking member formed between the first substrate and the overlapping portion, wherein the light blocking member includes a recessed portion corresponding to the overlapping portion of the first color filter and the second color filter. According to the present invention, the recessed portion is formed in the light blocking member provided in the overlapping portion of two or more color filters to reduce a step difference caused by the overlapping portion of the color filters, thereby preventing an alignment defect.

Abstract: A display device includes a substrate, a gate line connected to a gate driver, a reference voltage line, a data line crossing the gate line and the reference voltage line, a first thin film transistor including a first drain electrode and connected to the gate line and the data line, a second thin film transistor including a second drain electrode, a third thin film transistor connected to the gate line, the reference voltage line, and the second thin film transistor, and a pixel electrode including a first sub-pixel electrode connected to the first thin film transistor and a second sub-pixel electrode connected to the second thin film transistor. The first drain electrode overlaps the reference voltage line, and an area of a region in which the first drain electrode and the reference voltage line overlap each other increases in a direction toward the gate driver.

Abstract: A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.

Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

Abstract: A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.

Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.