Patents by Inventor Yong Tae Cho

Yong Tae Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7910438
    Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a first trench pattern, forming spacers over sidewalls of the first trench pattern, etching a bottom portion of the first trench pattern using the spacers as a barrier to form a second trench pattern, performing an isotropic etching on the second trench pattern to round sidewalls of the second trench pattern and form a bulb pattern, and forming a gate over a recess pattern including the first trench pattern, the rounded second trench pattern and the bulb pattern.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Jae-Seon Yu
  • Patent number: 7858476
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: December 28, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Suk-Ki Kim, Sang-Hoon Cho
  • Patent number: 7838361
    Abstract: A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: November 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Eun-Mi Kim
  • Publication number: 20100211992
    Abstract: A data security apparatus fragments original data into a plurality of data, blocks the fragmented data, and distributes and stores the blocked data over and in respective storage medium. The data security apparatus includes a storage having a first block, into which original data of a file is fragmented and blocked, distributed and stored, a security storage medium having a second block, into which the original data is fragmented and blocked, distributed and stored, and a distributed storage management module performing data interface among the storage, the security medium, and an operating system (OS) system, fragmenting and blocking the original data, and distributing and storing the blocked data over and in the storage and the security storage medium.
    Type: Application
    Filed: September 12, 2008
    Publication date: August 19, 2010
    Applicant: MILLENNIUM FORCE CO. LTD
    Inventors: Yong Tae Cho, Kyoung Mu Ryu
  • Publication number: 20100025806
    Abstract: In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.
    Type: Application
    Filed: December 30, 2008
    Publication date: February 4, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Hae-Jung Lee, Eun-Mi Kim, Kyeong-Hyo Lee
  • Patent number: 7642161
    Abstract: A method of fabricating a semiconductor device includes forming an isolation structure in a substrate to define an active region, forming a recess mask pattern over the isolation structure and the active region, etching the isolation structure exposed by the recess mask pattern to a certain depth, etching the substrate to form a recess pattern, and forming a gate electrode over the recess pattern.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: January 5, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Eun-Mi Kim
  • Patent number: 7575974
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate having a field oxide layer, etching the substrate to form a recess by using the hard mask pattern, forming a first conductive layer over the recess and the hard mask pattern, planarizing the first conductive layer, and forming a second conductive layer over the planarized first conductive layer.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: August 18, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Suk-Ki Kim, Yong-Tae Cho
  • Patent number: 7553767
    Abstract: A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a lower trench with approximately vertical edges; forming a device isolation layer disposed within the upper and lower trenches; and etching an active region of the substrate defined by the upper and lower trenches to a predetermined depth to form a recess pattern for a gate.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: June 30, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Eun-Mi Kim
  • Publication number: 20090163010
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a tungsten electrode over a substrate, performing a plasma oxidation process to form a capping layer on the surfaces of the gate patterns, forming an etch barrier layer over the substrate where the capping layer is formed, forming an interlayer dielectric layer to fill gap between the gate patterns, and etching the interlayer dielectric layer between the gate patterns to form a contact hole.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 25, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Sang-Rok OH, Hyun-Sik PARK, Yong- Tae CHO
  • Publication number: 20090130841
    Abstract: A method for forming a contact in a semiconductor device, comprises providing a substrate, forming a plurality of conductive patterns and a passivation layer surrounding the conductive patterns over the substrate, forming an insulation layer covering the conductive patterns and passivation layer, forming a mask pattern for a contact over the insulation layer, forming a first opening by performing an isotropic etch process on the insulation layer using the mask pattern as an etch mask, wherein the isotropic etch process is performed until the insulation layer meets the passivation layer, forming a barrier layer over a resultant structure of the first opening, exposing the insulation layer by performing an anisotropic etch process using the mask pattern as an etch mask, and forming a second opening exposing the substrate by performing a self aligned contact (SAC) process using the mask pattern and barrier layer as an etch mask.
    Type: Application
    Filed: June 27, 2008
    Publication date: May 21, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yong-Tae CHO, Jae-Kyun LEE, Sang- Rok OH
  • Publication number: 20090087960
    Abstract: A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 2, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yong-Tae CHO, Eun-Mi Kim
  • Patent number: 7507651
    Abstract: A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath the first recess to form a second recess, the second recess being wider and more rounded than the first recess; removing the spacer; and forming a gate pattern having a first portion buried into the first and second recesses and a second portion projecting over the substrate.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: March 24, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Suk-Ki Kim
  • Publication number: 20080160742
    Abstract: A method for fabricating a semiconductor device having a recess gate includes forming a first recess pattern by etching the substrate and a sidewall protection layer on sidewalls of the first recess pattern, forming a second recess pattern having a greater width than the first recess pattern by etching a certain portion of the substrate below a bottom portion of the first recess pattern, and forming a gate electrode filling the first and the second recess patterns.
    Type: Application
    Filed: December 24, 2007
    Publication date: July 3, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Yong-Tae CHO, Hae-Jung LEE
  • Publication number: 20080113500
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate having a field oxide layer, etching the substrate to form a recess by using the hard mask pattern, forming a first conductive layer over the recess and the hard mask pattern, planarizing the first conductive layer, and forming a second conductive layer over the planarized first conductive layer.
    Type: Application
    Filed: June 26, 2007
    Publication date: May 15, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Suk-Ki KIM, Yong-Tae CHO
  • Publication number: 20080102639
    Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 1, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Yong-Tae CHO, Suk-Ki KIM, Sang-Hoon CHO
  • Publication number: 20080102624
    Abstract: A method of fabricating a semiconductor device includes forming a hard mask pattern over a substrate, wherein the hard mask pattern exposes a recess region, performing a first etching process on the exposed recess region to form a first recess having sidewalls and to form passivation layers on the sidewalls of the first recess wherein the passivation layers are comprised of an etch reactant of the first etching process, and performing a second etching process on the substrate below the first recess to form a second recess.
    Type: Application
    Filed: December 29, 2006
    Publication date: May 1, 2008
    Inventors: Yong-Tae Cho, Suk-Ki Kim
  • Publication number: 20080081449
    Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a first trench pattern, forming spacers over sidewalls of the first trench pattern, etching a bottom portion of the first trench pattern using the spacers as a barrier to form a second trench pattern, performing an isotropic etching on the second trench pattern to round sidewalls of the second trench pattern and form a bulb pattern, and forming a gate over a recess pattern including the first trench pattern, the rounded second trench pattern and the bulb pattern.
    Type: Application
    Filed: June 29, 2007
    Publication date: April 3, 2008
    Inventors: Yong-Tae Cho, Jae-Seon Yu
  • Publication number: 20080003748
    Abstract: A method of fabricating a semiconductor device includes forming an isolation structure in a substrate to define an active region, forming a recess mask pattern over the isolation structure and the active region, etching the isolation structure exposed by the recess mask pattern to a certain depth, etching the substrate to form a recess pattern, and forming a gate electrode over the recess pattern.
    Type: Application
    Filed: December 26, 2006
    Publication date: January 3, 2008
    Inventors: Yong-Tae Cho, Eun-Mi Kim
  • Publication number: 20080003791
    Abstract: A method for fabricating a recess gate in a semiconductor device includes etching a substrate to form a first recess, etching the substrate at side portions of the first recess to form a second recess, and forming a gate insulation layer and a gate electrode over the second recess, wherein etching the substrate to form the second recess includes performing an isotropic etching process.
    Type: Application
    Filed: December 26, 2006
    Publication date: January 3, 2008
    Inventors: Yong-Tae Cho, Phil-Goo Kong
  • Publication number: 20070148934
    Abstract: A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath the first recess to form a second recess, the second recess being wider and more rounded than the first recess; removing the spacer; and forming a gate pattern having a first portion buried into the first and second recesses and a second portion projecting over the substrate.
    Type: Application
    Filed: April 27, 2006
    Publication date: June 28, 2007
    Inventors: Yong-Tae Cho, Suk-Ki Kim