Abstract: This invention provides a method of genetic testing that enables testing of a plurality of variation sites (SNPs) in a cost-effective and simple manner, allowing realization of genetic diagnosis in clinical settings. The SNP type of the nucleic acid sample is evaluated by: allowing a nucleic acid sample having an anchor sequence at its 5? end to hybridize to a support having, immobilized on its surface, a probe containing a sequence that is complementary to the target sequence (the SNP region); extending a complementary strand from the probe utilizing the nucleic acid sample as a template; dissociating and removing the nucleic acid sample from the extended probe; extending a complementary strand using the extended probe as a template and a primer having a sequence identical to the anchor sequence; and detecting pyrophosphoric acid generated via the primer extension, based on bioluminescence.

Abstract: The present invention intends to prevent the communication distance from becoming shorter with a reduction in size of a coil antenna to the chip size and with a consequent decrease of an induced voltage. According to the present invention there is provided a semiconductor chip having a coil antenna and a circuit surface and adapted to transmit and receive signals by radio to and from an external device. The semiconductor chip has a configuration for increasing an electromagnetic coupling coefficient between the coil antenna and the external device. According to a concrete example thereof, a magnetic material is disposed, the coil antenna is formed by a stacked structure comprising plural conductor layers and insulating layers superimposed one on another, or the coil antenna is disposed outside an external form of a circuit of the semiconductor chip.

Abstract: A wireless sensor chip suitable for the compact, high-sensitive, and low-cost examination apparatus for easily examining a biological material such as gene at low cost is provided. A sensor chip is formed on an SOI substrate, and an n type semiconductor layer on which a pMOS transistor is formed and a p type semiconductor layer on which an nMOS transistor is formed are isolated by a pn junction. Therefore, the p type semiconductor layer at the outermost portion (chip edge portion to be in contact with solution) is set to floating, and the maximum potential and the minimum potential of the chip are supplied to an n type semiconductor layer and a p type semiconductor layer inside the outermost portion, respectively. Also, the chip is covered with an ion impermeable insulating film for reducing the penetration of positive ions through the oxide layer.

Abstract: A communication system is provided which enhances communication stability, using chips on which function blocks are formed including sensor, chip ID, and radio transmission/reception functions. The sensor detects biological and chemical materials and physical and stoichiometric quantities such as temperature, pressure, and pH and the sensed results are transmitted to a reader by a radio frequency (RF) function. The chip with the sensor functions at a resonance frequency which is detected by the reader initially during a frequency sweep. No dedicated power source is essential to operate the chips, but instead the chips are triggered into transmitting by the radio frequency signals transmitted from the reader. The frequency and output of transmission from the reader to the chips are variable. Stable communication can be performed without being affected by variation in the chips characteristics depending on manufacturing quality.

Abstract: Concave and convex are formed on the substrate 1, the amorphous silicon layer 4 is formed on the metallic catalyst 3 dispersed and arranged in a dotted shape in the concave portion of the concave and convex, the crystal phases 5 having respective orientations from the metallic catalyst 3 are grown, further the crystal phases 5 are integrated with each other by continuing heat treatment and the polycrystalline silicon layer 6 is formed. A crystalline silicon semiconductor device and its method for fabrication which are costly advantageous and capable of efficiently forming the polycrystalline silicon layer of a predetermined thickness needed as a semiconductor device are provided.

Abstract: A system and method are provided for detecting biological and chemical material. To measure biological materials such as genes easily at low costs, the device for implementing a small-sized, high sensitive, economical measurement apparatus is provided. Probes appropriate for target biological materials are fixed on a chip, on which a sensor, identification number, and radio communication function are implemented, the captured targets are detected by the sensors, and the result of sensing are transferred to an external control unit by the radio communication function. The small-sized, high sensitivity measurement apparatus for detecting biological and chemical materials such as genes and measuring physical and chemical amounts such as temperature, pressure, pH, and the like can be implemented.

Abstract: A small sized, cost-effective genetic testing apparatus that provides high sensitivity testing, for performing genetic testing simply and at low cost. An optical sensor array for the apparatus and method for luminometric assay comprises a means that simultaneously selects 2 pixels and detects minute amounts of chemiluminescence by obtaining the differential output of the respective signals.

Abstract: To form an impurity diffusion layer on only one side of a semiconductor substrate at least one semiconductor substrate and at least one diffusion protecting plate are put close to each other and a first impurity diffusion is perfomed on them, or at least one semiconductor substrate and at least one diffusion protecting plate are put close to each other and a first impurity diffusion is performed on them and then the semiconductor substrate and the diffusion protecting plate are arranged such that those sides on which the impurity diffusion has been performed face each other and a second impurity diffusion is performed. The diffusion protecting plate may be replaced by a semiconductor substrate. The first and second impurity diffusions may be performed using an impurity of the same conductivity type.

Abstract: A photovoltaic cell produced by adhering a material for masking layer to a surface of a semiconductor substrate in pattern state to form the masking layer, and forming a dopant layer on the portion having no masking layer by gas phase diffusion or solid phase diffusion is high in photoelectric conversion efficiency and is effective for preventing lowering of minority carrier lifetime of the semiconductor substrate.

Abstract: Concave and convex are formed on the substrate 1, the amorphous silicon layer 4 is formed on the metallic catalyst 3 dispersed and arranged in a dotted shape in the concave portion of the concave and convex, the crystal phases 5 having respective orientations from the metallic catalyst 3 are grown, further the crystal phases 5 are integrated with each other by continuing heat treatment and the polycrystalline silicon layer 6 is formed. A crystalline silicon semiconductor device and its method for fabrication which are costly advantageous and capable of efficiently forming the polycrystalline silicon layer of a predetermined thickness needed as a semiconductor device are provided.

Abstract: A light concentrator photovoltaic module includes a medium having a light receiving plane, a plurality of photovoltaic elements arranged in a spaced relationship with the light receiving plane, and a light reflecting plane for conducting light incident upon the light receiving plane but is not directly received by the photovoltaic elements to the photovoltaic elements.

Abstract: Disclosed is a photovoltaic module including a plurality of concentrators each having a light-incident plane and a reflection plane, and photo detectors. Each photo detector is in contact with one of the concentrators. The module is capable of effectively trapping light and effectively generating power throughout the year even if the module is established such that sunlight at the equinoxes is made incident on the light-incident planes not in a perpendicular manner but instead obliquely, for example, in the case where the module is established in contact with a curved plane of a roof, or the like.

Abstract: Disclosed is a photovoltaic module including a plurality of concentrators each having a light-incident plane and a reflection plane, and photo detectors each being in contact with one of the concentrators, which is capable of effectively trapping light and effectively generating power throughout the year even if the module is established such that sunlight at the equinoxes is made incident on the light-incident planes not perpendicularly but obliquely from the right, upper side, for example, in the case where the module is established in contact with a curved plane of a roof or the like.

Abstract: There is disclosed a light-emitting device assembly use in a large-sized printhead. The assembly includes a number of insulating substrates including first and second substrates. A conducting layer is formed on each substrate. A conductive adhesive layer is formed on the conducting layer. The conducting layer on the first substrate extends close to the abutting end of this substrate. The conducting layer on the second substrate is set back a first distance from the abutting end of the second substrate. Light-emitting devices are disposed in the vicinity of the abutting end of the conducting layer on the second substrate. Light-emitting devices on the first substrate are made to protrude a second distance greater than the first distance from the abutting end of the first substrate. The light-emitting array protruding from the first substrate is made to bear against the light-emitting device array set back from the abutting end of the second substrate.

Abstract: A light receiving element having excellent characteristics, including high sensitivity and high response speed, can be achieved by a light element comprising unit structures each having two pn junction semiconductor layers, and a lightly doped semiconductor layer having low impurity density, lower than those of the p-type regions and the n-type regions of the two pn junction semiconductor layers, and which is sandwiched between the two pn junction semiconductor layers. The p-type regions of the pn junction semiconductor layers are disposed opposite to each other on opposite sides of the lightly doped semiconductor layer, respectively, and the n-type regions of the pn junction semiconductor layers are disposed opposite to each other on the opposite sides of the lightly doped semiconductor layer, respectively.

Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

Abstract: A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

Abstract: In a printed-wiring board produced by arranging a plurality of wiring circuit patterns on a printed-wiring board by screen printing and cutting out product regions corresponding to the wiring circuit patterns by punching them along the circumferences of the product regions, the printed-wiring board according to the present invention comprises deviation detecting patterns for determining whether or not the condition of deviation of the printed pattern is within an allowable limit, the deviation detecting patterns being printed at the time of the screen printing of the wiring circuit patterns in the vicinity of the position of the cut plane of the board for each product region of each wiring circuit pattern. Thereby, it is made possible to easily determine whether or not the condition of the pattern deviation is within a specified allowable limit.

Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has semiconductor elements such as MOSFETs and bipolar transistors formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

Abstract: A semiconductor integrated circuit device in which a wiring layer which supplies a predetermined operation voltage to an electronic circuit has a decreased parasitic impedance. The wiring layer is constituted by a first path and a second path that are connected in parallel between a connection pad and the electronic circuit, or a second wiring layer that constitutes an AC loop is formed close to the first wiring layer which supplies the operation voltage, or the above-mentioned two structures are employed in combination.