Abstract: A semiconductor storage device has a variable-stage charge pump, and a memory cell array to which an output from an output line of the variable-stage charge pump is fed. In the variable-stage charge pump, first and second charge pumps are connected in parallel between a common input bus and a common output bus. A first n-channel MOSFET is provided on a line connecting an output terminal of the first charge pump and the common output bus, and another n-channel MOSFET is provided on a line connecting the second charge pump and the common output bus. First switches are provided between the output terminal of the first charge pump and the first n-channel MOSFET, and between the input terminal of the second charge pump and the second switch. A second switch is provided on a line connecting an input terminal of the second charge pump and the common input bus.

Abstract: A semiconductor storage device includes a voltage supply circuit generating a voltage of 5V, a voltage polarity inversion circuit generating a voltage of −5V, a select-and-connect circuit supplying the voltages of 5V and −5V to a memory cell array, a 5 V voltage level detection circuit detecting the voltage derived from the voltage supply circuit, and a −5 V voltage level detection circuit detecting the voltage derived from the voltage polarity inversion circuit. Absolute values of the voltages detected by the voltage level detection circuits are lower than ever before. This allows a gate insulation film to be thinner. A memory-function film is formed on both sides of a gate electrode in the semiconductor storage device. This also make the gate insulation film thinner. The thin gate insulation film suppresses the short-channel effect, so that each memory element of the memory cell array is miniaturized.

Abstract: A semiconductor memory device including: a memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and an amplifier, the memory cell and the amplifier being connected to each other so that an output of the memory cell is inputted to the amplifier.

Abstract: A latch circuit includes a first circuit including an N-MOS transistor having a first electrode receiving a signal, a second electrode outputting the signal, a gate electrode, and a P-well, and a first inverter including input and output terminals. The second electrode of the N-MOS transistor is electrically connected to the input terminal of the first inverter, and the gate electrode of the N-MOS transistor is electrically connected to the P-well of the N-MOS transistor.