Abstract: A method and an apparatus for converting a frame phase of a signal having a frame structure specified in the CCITT recommendations which contains N (N: an integer 2 or above) pieces of frames applied with time-division/multiplex, in which the N pieces of frames are given to N pieces of memories, respectively, a write address is given independently to each memory so that the N pieces of frames are written in the respective memories in a same phase as the phase in the signal, a read address is given independently to each memory so that the N pieces of frames are read out of the respective memories in a same phase as the write phase, a difference between a write address and a read address in each memory is set identical under an initial state, and justification is executed for a frame which is read out of the memory in accordance with a difference between existing write address and read address in each memory, whereby to perform frame phase conversion while maintaining relative phase among respective frames.

Abstract: A method for transmitting virtual path failure information in an asynchronous transfer mode network the method includes performing search against a table storing virtual paths being used for generating failure indicative cells for respective ones of the virtual paths when failure of a transmission line is detected. The generated failure indicative cells are transmitted to all of the other apparatuses connected in downstream signal transmitting directions through the virtual path sequentially for a number of predetermined times, and subsequently, intermittently with an interval of a given period of time. When failure is removed, a normal cell is immediately transmitted.

Abstract: In a communication apparatus using an asynchronous transfer mode, there is provided a system switching method, and apparatus, without loss of signal for performing cell multiplexing or cell switching in a duplex system including a primary system and a standby system. In system switching, control information for switching between the primary system and the standby system is prepared. When a cell is inputted to the communication apparatus, the prepared control information is appended in a header portion of the cell. The cell with control information appended thereto is transmitted to the duplex system including the primary system and the standby system. On the basis of the control information, cell transfer of each system is controlled.

Abstract: A frame aligner and a method and system for control thereof, in which the frame alignment is executed while assuring TSSI (Time Slot Sequence Integrity). In a system for transmitting a plurality of low-speed signals having a frame structure in a high-speed frame, a plurality of candidates for a write start phase for a frame aligner memory are set, and by accessing a common phase memory storing a write start phase shared by low-speed signals requiring phase matching therebetween of all the low-speed signals stored in the high-speed frame, a write start phase is selected from among the candidates for the write start phase for the frame aligner memory.

Abstract: An ATM switch has a plurality of concentration space-division switches each constituted with an S-stage connection of switch modules. Each of the switch modules includes M buffers and a selector for selecting an arbitrary one of outputs from the M buffers. Each stage includes switch modules of which the number is obtained by multiplying by at most M a number of switch modules disposed in a stage succeeding thereto. The S stages include a final stage constituted with a switch module.

Abstract: A CMI block synchronization circuit includes a clock deriving circuit, CMI decoding circuit, signal selection determining circuit and a selection circuit. In the clock deriving circuit, a clock CLK.sub.o having the same phase as a binary signal and a clock CLK.sub..pi. having a phase which is different 180.degree. from the clock CLK.sub.o are derived from an inputted CMI code signal. In the CMI decoding circuit, the inputted CMI code signal is decoded by using the clocks derived and violating bits are detected. In the signal selection determining circuit, the clocks CLK.sub.o and CLK.sub..pi. are counted respectively. Only when one of the count values is equal to or higher than a setting value and another count value is lower than another setting value is it regarded that a block asynchronization is caused in decoding the CMI code signal.

Abstract: The present invention relates to an add drop multiplexer related to the synchronous multiplexing method, and includes a pass-through line connecting unit, which is driven by a timing signal extracted from a signal received through a transmission line and effects branching and insertion of the line as well as connection of pass-through lines at multiplexed levels; an office line connecting unit having an office interface function for each of other devices in a same office; a first frame aligner connecting multiplex branched signals from the pass-through line connecting unit with the office line connecting unit; and a second frame aligner connecting multiplex inserted signals from the office line connecting unit with the pass-through line connecting unit.