Patents by Inventor Yoshihiro Miyazaki
Yoshihiro Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10978371Abstract: A semiconductor device including an insulated circuit board on which a semiconductor chip is mounted, and a housing implemented by a plurality of side-walls including at least a first pair of facing side-walls, each of the facing side-walls having joint edges configured to be jointed with the insulated circuit board, and each of the joint edges has an arc-shape such that a center in an extending direction of the joint edge protrudes toward the insulated circuit board more than both ends of the extending direction of the joint edge.Type: GrantFiled: January 22, 2019Date of Patent: April 13, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kenshi Kai, Rikihiro Maruyama, Yoshihiro Miyazaki
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Patent number: 10661450Abstract: A finger mechanism includes a base portion and a plurality of finger portions supported by the base portion, wherein each of the finger portions includes a first bone member, a second bone member rotatably coupled to one end portion of the first bone member, and a pair of third bone members each being rotatably coupled to another end portion of the first bone member and the base portion, and forming a parallel link mechanism between the first bone member and the base portion.Type: GrantFiled: October 19, 2018Date of Patent: May 26, 2020Assignee: SQUSE Inc.Inventors: Yoshihiro Miyazaki, Shota Okuyama, Yuya Wada
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Publication number: 20200156260Abstract: A transfer apparatus includes a finger mechanism configured to grasp an outer circumferential face of an object, wherein the finger mechanism is equipped with a plurality of finger portions supported by a base portion, each of the finger portions includes a first bone member, a second bone member rotatably coupled to one end portion of the first bone member, and a pair of third bone members, each of which is rotatably coupled to the other end portion of the first bone member and the base portion, whereby a parallel link mechanism is formed between the first bone member and the base portion, and the finger mechanism transfers the grasped object to a containing box.Type: ApplicationFiled: October 8, 2019Publication date: May 21, 2020Inventors: Toru Takasaki, Yuya Wada, Yoshihiro Miyazaki, Yoshinobu Fukushima
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Patent number: 10398036Abstract: After a contact component is disposed in a concave joint space, when a solder solidifies, the solder thickness of the solder in the joint space is kept. Thus, a contact area between the contact component and the solder is kept, and the solder thickness of the solder that joins the contact component and a conductive pattern is kept. In addition, since an appropriate amount of the solder is kept in the joint space, an extra amount of solder does not need to be applied in advance. As a result, there is prevented creeping up of the solder into a hollow hole of the contact component, caused by the heat applied when the contact component is joined to the conductive pattern.Type: GrantFiled: January 31, 2018Date of Patent: August 27, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Kenshi Kai, Rikihiro Maruyama, Yoshihiro Miyazaki
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Publication number: 20190160692Abstract: A finger mechanism includes a base portion and a plurality of finger portions supported by the base portion, wherein each of the finger portions includes a first bone member, a second bone member rotatably coupled to one end portion of the first bone member, and a pair of third bone members each being rotatably coupled to another end portion of the first bone member and the base portion, and forming a parallel link mechanism between the first bone member and the base portion.Type: ApplicationFiled: October 19, 2018Publication date: May 30, 2019Inventors: Yoshihiro Miyazaki, Shota Okuyama, Yuya Wada
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Publication number: 20190157183Abstract: A semiconductor device including an insulated circuit board on which a semiconductor chip is mounted, and a housing implemented by a plurality of side-walls including at least a first pair of facing side-walls, each of the facing side-walls having joint edges configured to be jointed with the insulated circuit board, and each of the joint edges has an arc-shape such that a center in an extending direction of the joint edge protrudes toward the insulated circuit board more than both ends of the extending direction of the joint edge.Type: ApplicationFiled: January 22, 2019Publication date: May 23, 2019Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kenshi KAI, Rikihiro Maruyama, Yoshihiro Miyazaki
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Patent number: 10286561Abstract: A finger mechanism includes a first bone member and a second bone member, a first rotation core that rotatably couples the first bone member and the second bone member at end portions in a direction of a length thereof, an extensor tendon that is disposed on a side where the second bone member extends with respect to the first bone member and extends in the direction of the length of the first bone member and the second bone member, a first extensor tendon guide that is provided on both of the first bone member and the second bone member and guides the extensor tendon so that the extensor tendon is in contact with a part of a surface of the first rotation core, an extensor that is connected to the extensor tendon and extends and flexes the extensor tendon, a flex tendon that is disposed on a side where the first bone member flexes with respect to the second bone member and extends in the direction of the length of the first bone member and the second bone member, a first flex tendon guide that is provided onType: GrantFiled: September 21, 2018Date of Patent: May 14, 2019Assignee: SQUSE Inc.Inventors: Yoshihiro Miyazaki, Kanami Toui
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Publication number: 20190099899Abstract: A finger mechanism includes a first bone member and a second bone member, a first rotation core that rotatably couples the first bone member and the second bone member at end portions in a direction of a length thereof, an extensor tendon that is disposed on a side where the second bone member extends with respect to the first bone member and extends in the direction of the length of the first bone member and the second bone member, a first extensor tendon guide that is provided on both of the first bone member and the second bone member and guides the extensor tendon so that the extensor tendon is in contact with a part of a surface of the first rotation core, an extensor that is connected to the extensor tendon and extends and flexes the extensor tendon, a flex tendon that is disposed on a side where the first bone member flexes with respect to the second bone member and extends in the direction of the length of the first bone member and the second bone member, a first flex tendon guide that is provided onType: ApplicationFiled: September 21, 2018Publication date: April 4, 2019Inventors: Yoshihiro Miyazaki, Kanami Toui
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Publication number: 20180279484Abstract: After a contact component is disposed in a concave joint space, when a solder solidifies, the solder thickness of the solder in the joint space is kept. Thus, a contact area between the contact component and the solder is kept, and the solder thickness of the solder that joins the contact component and a conductive pattern is kept. In addition, since an appropriate amount of the solder is kept in the joint space, an extra amount of solder does not need to be applied in advance. As a result, there is prevented creeping up of the solder into a hollow hole of the contact component, caused by the heat applied when the contact component is joined to the conductive pattern.Type: ApplicationFiled: January 31, 2018Publication date: September 27, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kenshi KAI, Rikihiro MARUYAMA, Yoshihiro MIYAZAKI
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Patent number: 6453391Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect the same operation in synchronism with each other.Type: GrantFiled: June 18, 2001Date of Patent: September 17, 2002Assignee: Hitachi, Ltd.Inventors: Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki
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Publication number: 20010032301Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect a same operation in synchronism with each other.Type: ApplicationFiled: June 18, 2001Publication date: October 18, 2001Applicant: Hitachi, Ltd.Inventors: Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki
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Patent number: 6138248Abstract: A computer and a backup computer exchange periodic report signal transmissions by way of SVP115. When there is no periodic report signal transmission from the main computer, the backup computer makes a main computer status inquiry and if one location is malfunctioning resets the main computer by way of the SVP115 and continues the processing. When permanent damage is present, the SVP115 continually resets the main computer and controls MOS switches of the common disk unit to isolate the SCSI from the main computer and continue the main computer processing.Type: GrantFiled: December 30, 1997Date of Patent: October 24, 2000Assignee: Hitachi, Ltd.Inventors: Masahiko Saito, Hidehito Takewa, Kenichi Kurosawa, Yoshihiro Miyazaki, Shigenori Kaneko
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Patent number: 6032265Abstract: A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-operating CPU portion requiring sophisticated packaging technology, but in the low-speed interface between the CPUs and the I/O bus adapters. This allows the CPUs and I/O bus adapters to be shared by ordinary data processors, workstations, or personal computers while implementing a fault-tolerant computer system. If a one-shot hardware fault occurs in a CPU or in an I/O bus adapter, the faulty component is disconnected from the system so that the system will operate uninterruptedly.Type: GrantFiled: July 18, 1996Date of Patent: February 29, 2000Assignee: Hitachi, Ltd.Inventors: Hiroshi Oguro, Shinichiro Yamaguchi, Yoshihiro Miyazaki, Soichi Takaya, Masataka Hiramatsu, Nobuo Akeura
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Patent number: 6003116Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which carry out the same operation in synchronism with each other.Type: GrantFiled: October 29, 1996Date of Patent: December 14, 1999Assignee: Hitachi, Ltd.Inventors: Yuuichiro Morita, Tetsuaki Nakamikawa, Shinichiro Yamaguchi, Naoto Miyazaki, Shin Kokura, Yoshihiro Miyazaki
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Patent number: 5852728Abstract: The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.Type: GrantFiled: January 11, 1996Date of Patent: December 22, 1998Assignee: Hitachi, Ltd.Inventors: Koji Matsuda, Soichi Takaya, Yoshihiro Miyazaki, Kenichi Kurosawa, Shinichiro Yamaguchi, Sako Ishikawa, Akira Yamagiwa, Masao Inoue, Kenji Kashiwagi
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Patent number: 5841963Abstract: A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.Type: GrantFiled: May 21, 1997Date of Patent: November 24, 1998Assignee: Hitachi, Ltd.Inventors: Tetsuaki Nakamikawa, Shin Kokura, Kenichi Kurosawa, Shinichiro Yamaguchi, Yoshihiro Miyazaki, Hiroshi Ohguro
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Patent number: 5737513Abstract: A method of verifying operation concurrence in maintenance/replacement of twin CPUs employed in a dual-CPU computer wherein a replacement CPU with an initial fault may have been installed by mistake during on-line maintenance/replacement work and a system therefor are disclosed whereby a failure which, without the method and the system, would occur due to the initial fault of the replacement CPU during a dual subsystem synchronous operation carried out thereafter by the computer can be prevented from entailing a system down on both the subsystems.Type: GrantFiled: May 20, 1996Date of Patent: April 7, 1998Assignees: Hitachi, Ltd., Hitachi Information & Control Systems Inc.Inventors: Koji Matsuda, Yoshihiro Miyazaki, Soichi Takaya, Kazuhiro Hyuga, Nobuo Akeura, Shinichiro Yamaguchi, Naoto Miyazaki, Satoru Kayukawa
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Patent number: 5551007Abstract: A multiple common memory system is provided in which at least three CPUs share at least two common memories each storing one and the same content. Each of the first and second CPUs contains a respective one of the two common memories, and each of the first and second CPUs has an arrangement to access the common memory therein at the time of requesting a read access to a common memory. Other CPUs in the system do not contain common memories, but do include arrangements to access the common memory of the first or second CPU at the time of requesting a read access to a common memory.Type: GrantFiled: September 16, 1993Date of Patent: August 27, 1996Assignee: Hitachi, Ltd.Inventors: Yoshihiro Miyazaki, Yoshiaki Takahashi, Manabu Araoka, Soichi Takaya, Hiroaki Fukumaru
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Patent number: 5418404Abstract: In a data processing device, when exchanging a plug-in package with another without breaking the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.Type: GrantFiled: June 14, 1994Date of Patent: May 23, 1995Assignees: Hitachi, Ltd., Hitachi Process Computer Engineering, Inc.Inventors: Manabu Araoka, Yoshiaki Takahashi, Atsushi Shikama, Yoshihiro Miyazaki, Tomoaki Nakamura, Masayuki Sakata
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Patent number: 5345566Abstract: A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses.Type: GrantFiled: January 24, 1992Date of Patent: September 6, 1994Assignee: Hitachi, Ltd.Inventors: Masayuki Tanji, Yoshihiro Miyazaki, Hiroaki Fukumaru, Syoji Yamaguchi, Koji Masui, Hisao Ogawa