Abstract: In a data processing device, when exchanging a plug-in package with another without breaking off the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.

Abstract: A data processing device which includes a common memory connecting mechanism which is located between a memory bus to which copyback cache is connected, and a common memory. The common memory connecting mechanism includes a slave type transfer mechanism which directly assesses the common memory bypassing the cache and processes thereof, and a data mover which transfers data between the common memory and main memory.

Abstract: Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

Abstract: A co-processor control method intended to speed up data transfer linkage between the co-processor and memory when the co-processor is activated by the main processor, in such a way that the main processor issues an active control signal to the co-processor in the cycle of reading out an operand in the memory onto the data bus by being addressed by the main processor so that the operand on the data bus is directly delivered to the co-processor.

Abstract: Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

Abstract: A data processor for execution of tagged data and tagless data has a decoder for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part for extracting the tag part from data on a data bus, a plurality of tag part storing registers for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

Abstract: The present application invention relates to a method for restarting execution of an instruction interrupted due to a page fault. When a page fault occurs during an execution of an instruction, the pertinent page is loaded from an external storage into the main memory and then the access which has caused the page fault is executed again. After N steps of the microprogram that has executed the page fault access, the page fault exception processing is initiated and at the save/restore operation of the content of the microprogram counter, the content of the microprogram is decremented by N, thereby restarting the execution of the instruction beginning from the step of the microprogram which has achieved the page fault access.

Abstract: A microprogram controlled data processing apparatus executes multi-operand instructions in which one or more operand specifiers are provided for specifying the addressing for each operand independently from the operation code of the instruction. An instruction execution unit receives a top address of a microprogram from a decoding unit, a ready status signal and a signal from the decoding unit indicating whether a destination of an operand is in a general purpose register or in a memory unit, and writes an operand into a destination address of a register on the memory unit under control of a microprogram. Because the destination of the operand is indicated by the instruction decoding unit, it is not necessary to determine this information by microinstruction execution, with the result that execution of the instruction can be performed at high speed.

Abstract: A display system having a frame buffer comprising a plurality of memory planes, a display device for visually displaying images written into the frame buffer, and a controller for controlling image data operations. The display system is provided with an extended raster operation circuitry comprising an intraplane operation unit and an interplane operation unit. Operation results of the circuitry are written back to the frame buffer. The respective operation units perform operations specified by the controller. The intraplane operation unit performs operations on image data in each of the memory planes, separately, while the interplane operation unit performs operations on image data in at least two memory planes selected by the controller. There are no restrictions as to the positional relation between the intraplane operation unit and the interplane operation unit.

Abstract: A multicomputer system having dual common memories in which specified address areas are set within the common memories. The specified address areas are accessible irrespective of whether a CPU is in an online mode or a debug mode, while any area other than the specified address areas is accessible only when the function mode of the common memory is in agreement with the access mode of the CPU. In correspondence with each CPU, addresses to be used by the CPU are divided into a plurality of groups of addresses, and the access modes are set for the respective address groups.

Abstract: Method and apparatus for controlling interruption of a processor. When an external interrupt request having a higher priority level than a current program level is detected in the course of the execution of an instruction, the processing is interrupted and an interexecution interruption is issued. The program level is fixed in this interruption so that the interrupt request is processed as a normal interrupt request at an interruption destination, and the processing is resumed from the interrupted point at a second return instruction after the interrupt processing.

Abstract: A dual memory system consists of two memory units each having volatile memory devices, backup power storage means and backup monitoring facility which memorizes a signal indicative of whether backup is successful or failing. When the contents of one memory unit are copied to another memory unit, the receiving memory unit has the monitor signal in a state which is made coincident with the signal state of the sending memory unit. Consequently, the receiving memory unit will have the same state of the monitor signal as of the sending memory unit at the end of copying, and thus both memory units are in a successful backup state only when the sending memory unit is in a successful backup state.

Abstract: A digital differential analyzer (DDA) is connected through a direct memory access bus (DMA bus) to a host processor so as to receive an operation defining parameter and data, thereby to process a differential analysis as a digital operation.The DDA has mainly an arithmetic processor for DDA operation, and a control processor for performing the control concerning DMA to the host processor and the start and end control of the DDA operation which is performed by the arithmetic processor. This DDA decreases the amount of program to be processed by the host processor.