Abstract: A display device where low power consumption is realized without lowering aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL and a voltage supply line VSL, respectively. The second switch circuit 23 is a series circuit including a transistor T1 and diode D1. A control terminal of the transistor T1, a second terminal of the transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the transistor T2 are connected to a boost line BST and a reference line REF, respectively.

Abstract: An embodiment of the present invention provides a liquid crystal display device. In each pixel circuit, a pixel electrode is connected to a source line via a third transistor. When a refreshing circuit performs a refreshing operation, a boosting signal line is supplied with a voltage pulse. If the pixel electrode is at a high voltage level at this time point, a voltage at a node is boosted and a first transistor turns ON to supply a refreshing voltage to the pixel electrode. If the pixel electrode is at a low voltage level, there is no boost, and the first transistor stays in OFF state, so a node assumes a voltage which is given by an off-resistance ratio of the first and the third transistors, and this voltage is supplied to the pixel electrode.

Abstract: A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively.

Abstract: Provided is a nonvolatile memory 10 having a selective gate SG formed below a silicon layer 14, which is to be a channel region formed between a source region S and a drain region D of a transistor, through a gate insulating film 15 between the silicon layer and the selective gate, a floating gate FG formed on a part over the silicon layer 14 through a gate insulating film 16, and a control gate CG connected to the floating gate FG. The selective gate SG has one end overlapping the source region S through the gate insulating film 15, and the floating gate FG has one end overlapping the drain region D through the gate insulating film 16, and the other end separated from the source region S and overlapping the silicon layer 14 through the gate insulating film 16. Thus, a nonvolatile memory whose performance is not deteriorated even when it is formed on an insulating substrate having a low heat dissipating characteristic can be achieved.

Abstract: A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively.

Abstract: In a display device, a liquid crystal capacitive element is sandwiched between a pixel electrode and an opposite electrode. The pixel electrode, one end of a first switch circuit, one end of a second switch circuit and a first terminal of a second transistor form an internal node. The other terminals of the first switch circuit and the second switch circuit are connected to a source line. The second switch circuit is a series circuit composed of a first transistor and a diode. A control terminal of the first transistor, a second terminal of the second transistor and one end of a boost capacitive element form an output node. The other end of the boost capacitive element and the control terminal of the second transistor are connected to a boost line and a reference line, respectively.

Abstract: A pixel circuit includes a display element unit including a unit liquid crystal display element having a liquid crystal layer between a pixel electrode and a counter electrode, a capacitor element having a tunnel insulating film between first and second electrodes wherein a tunnel current flows between the electrodes when a predetermined high voltage is applied between the electrodes, and a switch circuit having a first terminal connected to the second electrode of the capacitor element, a second terminal connected to a data signal line, and a control terminal connected to a scanning signal line, the control terminal controlling electrical connection between the first and second terminals. A voltage corresponding to pixel data with a voltage of the counter electrode being a reference is held in an internal node connecting the pixel electrode and the first electrode of the capacitor element.

Abstract: A liquid crystal display device includes a data signal line driving circuit which separately drives data signal lines of an active matrix pixel array. One vertical period is divided into a scanning period and a non-scanning period. The data signal line driving circuit applies a signal voltage corresponding to the pixel data having the same polarity to the same data signal line with a predetermined fixed potential as a reference regardless of an order of a selected scanning signal line in the scanning period, and applies an intermediate voltage between maximum and minimum values of pixel voltages to each data signal line in the non-scanning period, the pixel voltages being respectively held in the pixel electrodes of the pixels connected to each data signal line.

Abstract: A nonvolatile semiconductor memory device having a source-side-injected split-gate type of nonvolatile memory cell which can be formed by a one-layer polysilicon CMOS process is provided. A memory cell includes a first memory cell unit including first and second diffusion regions formed on a semiconductor substrate surface, and first and second gate electrodes separately formed through a gate insulation film on a first channel region between the first and second diffusion regions, a second memory cell unit including third and fourth diffusion regions formed on the semiconductor substrate surface, and a third gate electrode formed through a gate insulation film on a second channel region between the third and fourth diffusion regions, and a control terminal. The first to third gate electrodes are formed of the same electrode material layer. The second and third gate electrodes are electrically connected to form a floating gate capacitively coupled to the control terminal.

Abstract: A display device includes liquid crystal capacitor element interposed between a pixel electrode and a counter electrode. The pixel electrode, one terminals of a first switch circuit and a second switch circuit, and a first terminal of a second transistor form an internal node. The other terminals of the first switch circuit is connected to the source line. The other terminal of the second switch circuit is connected to the voltage supply line and is configured by a series circuit of transistors. A control terminal of the transistor, a second terminal of the transistor, and one terminal of a boost capacitor element form an output node. The other terminal of the boost capacitor element, the control terminal of the transistor, and the control terminal of the transistor are connected to a boost line, a reference line, and a selecting line, respectively.

Abstract: A display device which realizes constant display having multiple tones with low power consumption is provided.

Abstract: A display device in which a pixel voltage is held at low power consumption without any influence from fluctuation in threshold voltage is provided. A liquid crystal capacitor element (Clc) is formed between a pixel electrode (20) and a counter electrode (80). A counter voltage (Vcom) is applied to the counter electrode (80). The pixel electrode (20), one ends of a first switch circuit (22) and a second switch circuit (23), and a first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switch circuit (22) is connected to a source line (SL). The second switch circuit (23) has the other end connected to a voltage supply line (VSL) and is a series circuit of transistors (T1 and T2). A control terminal of the transistor (T1), a second terminal of the transistor (T2), and one end of the boost capacitor element (Cbst) form an output node (N2).

Abstract: A display device which can prevent deterioration of a liquid crystal and reduction in display quality at low power consumption without lowering an aperture ratio is provided. An opposite voltage (Vcom) is applied to an opposite electrode (80) of a liquid crystal capacitive element (Clc). One ends of a pixel electrode (20), a first switch circuit (22), a second switch circuit (23), and a first terminal of a second transistor (T2) form an internal node (N1). The other ends of the first switch circuit (22) and the second switch circuit (23) are connected to a source line (SL) and a voltage supply line (VSL), respectively. A control terminal of a first transistor (T1) in the second switch circuit (23), a second terminal of the second transistor (T2), and one end of a boost capacitive element (Cbst) form an output node (N2). The other end of the boost capacitive element (Cbst) and the control terminal of the second transistor (T2) are connected to a boost line (BST) and a reference line (REF), respectively.

Abstract: Disclosed is a display device that can achieve a reduction of power consumption without deteriorating the aperture ratio. A liquid crystal capacitance element (Clc) is formed by being sandwiched between a pixel electrode (20) and an opposite electrode (80). The pixel electrode (20), one end of a first switching circuit (22), one end of a second switching circuit (23), and the first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switching circuit (22) and the other end of the second switching circuit (23) are connected to a source line (SL). The second switching circuit (23) includes a series circuit of a transistor (T1) and a diode (D1), and an output node (N2) is formed of the control terminal of the transistor (T1), the second terminal of the transistor (T2), and one end of a boost capacitance element (Cbst).

Abstract: A display device which realizes a multi-gradation constant display with low power consumption is provided.

Abstract: In a display device including a pixel circuit having a transistor with a low electron mobility, low power consumption is realized without decreasing an aperture ratio. An liquid crystal capacitor element (Clc) is formed between a pixel circuit (20) and a counter electrode (80). One ends of the pixel electrode (20), a first switch circuit (22), and a second switch circuit (23) and a first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switch circuit (22) is connected to a source line (SL). The second switch circuit (23) has the other end connected to a voltage supply line (VSL), and is a series circuit of transistors (T1 and T3). A control terminal of the transistor (T1), a second terminal of the transistor (T2), and one end of the boost capacitor element (Cbst) form an output node (N2). The other end of the boost capacitor element (Cbst) and the control terminal of the transistor (T2) are connected to a selecting line (SEL) and a reference line REF, respectively.

Abstract: A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively.

Abstract: A display device in which a pixel voltage is held at low power consumption without any influence from fluctuation in threshold voltage is provided. A liquid crystal capacitor element (Clc) is formed between a pixel electrode (20) and a counter electrode (80). A counter voltage (Vcom) is applied to the counter electrode (80). The pixel electrode (20), one ends of a first switch circuit (22) and a second switch circuit (23), and a first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switch circuit (22) is connected to a source line (SL). The second switch circuit (23) has the other end connected to a voltage supply line (VSL) and is a series circuit of transistors (T1 and T2). A control terminal of the transistor (T1), a second terminal of the transistor (T2), and one end of the boost capacitor element (Cbst) form an output node (N2).

Abstract: Disclosed is a display device that can achieve a reduction of power consumption without deteriorating the aperture ratio. A liquid crystal capacitance element (Clc) is formed by being sandwiched between a pixel electrode (20) and an opposite electrode (80). The pixel electrode (20), one end of a first switching circuit (22), one end of a second switching circuit (23), and the first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switching circuit (22) and the other end of the second switching circuit (23) are connected to a source line (SL). The second switching circuit (23) includes a series circuit of a transistor (T1) and a diode (D1), and an output node (N2) is formed of the control terminal of the transistor (T1), the second terminal of the transistor (T2), and one end of a boost capacitance element (Cbst).

Abstract: A display device where low power consumption is realized without lowering aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL and a voltage supply line VSL, respectively. The second switch circuit 23 is a series circuit including a transistor T1 and diode D1. A control terminal of the transistor T1, a second terminal of the transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the transistor T2 are connected to a boost line BST and a reference line REF, respectively.