Patents by Inventor Yoshinobu Nakagome
Yoshinobu Nakagome has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060250876Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.Type: ApplicationFiled: July 11, 2006Publication date: November 9, 2006Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Publication number: 20060208315Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.Type: ApplicationFiled: May 24, 2006Publication date: September 21, 2006Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi
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Patent number: 7082074Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.Type: GrantFiled: July 19, 2005Date of Patent: July 25, 2006Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Patent number: 7072202Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.Type: GrantFiled: March 21, 2005Date of Patent: July 4, 2006Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Patent number: 7072242Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: GrantFiled: October 18, 2004Date of Patent: July 4, 2006Assignee: Renesas Technology Corp.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Patent number: 7061053Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.Type: GrantFiled: August 31, 2004Date of Patent: June 13, 2006Assignee: Hitachi, Ltd.Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi
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Publication number: 20060087909Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: ApplicationFiled: December 12, 2005Publication date: April 27, 2006Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Publication number: 20050249017Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.Type: ApplicationFiled: July 19, 2005Publication date: November 10, 2005Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Publication number: 20050231991Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.Type: ApplicationFiled: March 21, 2005Publication date: October 20, 2005Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Publication number: 20050083096Abstract: A semiconductor integrated circuit includes a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit corresponds to the frequency of the reference clock signal.Type: ApplicationFiled: November 8, 2004Publication date: April 21, 2005Inventors: Hiroyuki Mizuno, Takahiro Nagano, Yoshinobu Nakagome
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Patent number: 6870790Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.Type: GrantFiled: December 2, 2003Date of Patent: March 22, 2005Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Publication number: 20050052944Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: ApplicationFiled: October 18, 2004Publication date: March 10, 2005Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Publication number: 20050023615Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.Type: ApplicationFiled: August 31, 2004Publication date: February 3, 2005Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi
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Patent number: 6819158Abstract: A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit is correspondent to the frequency of the reference clock signal.Type: GrantFiled: May 29, 2003Date of Patent: November 16, 2004Assignee: Renesas Technology Corp.Inventors: Hiroyuki Mizuno, Takahiro Nagano, Yoshinobu Nakagome
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Patent number: 6819626Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: GrantFiled: July 8, 2003Date of Patent: November 16, 2004Assignee: Renesas Technology Corp.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Publication number: 20040217776Abstract: A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.Type: ApplicationFiled: June 3, 2004Publication date: November 4, 2004Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
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Patent number: 6787841Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.Type: GrantFiled: August 29, 2003Date of Patent: September 7, 2004Assignee: Hitachi, Ltd.Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi
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Publication number: 20040109383Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.Type: ApplicationFiled: December 2, 2003Publication date: June 10, 2004Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Patent number: 6747509Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.Type: GrantFiled: January 15, 2002Date of Patent: June 8, 2004Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
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Publication number: 20040041209Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.Type: ApplicationFiled: August 29, 2003Publication date: March 4, 2004Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi