Patents by Inventor Yoshinobu Nakagome
Yoshinobu Nakagome has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20010008497Abstract: A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.Type: ApplicationFiled: January 16, 2001Publication date: July 19, 2001Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Publication number: 20010002177Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.Type: ApplicationFiled: December 21, 2000Publication date: May 31, 2001Applicant: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Takao Watanabe, Yoshinobu Nakagome
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Publication number: 20010001262Abstract: A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.Type: ApplicationFiled: January 16, 2001Publication date: May 17, 2001Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Patent number: 6212127Abstract: Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.Type: GrantFiled: May 1, 2000Date of Patent: April 3, 2001Assignee: Hitachi, Ltd.Inventors: Seiji Funaba, Yoji Nishio, Yuichi Okuda, Yoshinobu Nakagome
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Patent number: 6195294Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.Type: GrantFiled: July 11, 2000Date of Patent: February 27, 2001Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Takao Watanabe, Yoshinobu Nakagome
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Patent number: 6195306Abstract: A semiconductor device has a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits are deactivated.Type: GrantFiled: April 12, 1999Date of Patent: February 27, 2001Assignee: Hitachi, Ltd.Inventors: Masashi Horiguchi, Masayuki Nakamura, Sadayuki Ohkuma, Kazuhiko Kajigaya, Yoshinobu Nakagome
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Patent number: 6166577Abstract: A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit is correspondent to the frequency of the reference clock signal.Type: GrantFiled: October 12, 1999Date of Patent: December 26, 2000Assignee: Hitachi, Ltd.Inventors: Hiroyuki Mizuno, Takahiro Nagano, Yoshinobu Nakagome
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Patent number: 6111793Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.Type: GrantFiled: September 22, 1998Date of Patent: August 29, 2000Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Takao Watanabe, Yoshinobu Nakagome
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Patent number: 6107869Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.Type: GrantFiled: June 11, 1998Date of Patent: August 22, 2000Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
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Patent number: 6104056Abstract: A field-effect semiconductor element implemented with a reduced number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature. In accordance with one embodiment, a carrier confinement region, isolated from a channel and a gate of the semiconductor FET element, is provided to operate as a storage node for trapping the carrier or carriers.Type: GrantFiled: July 30, 1998Date of Patent: August 15, 2000Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi
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Patent number: 6072354Abstract: In a semiconductor device having a plurality of output circuits such as a semiconductor memory device, a drive signal having a boosted voltage level which is produced from a boosting circuit is applied to a gate of a low-level outputting MOS transistor in the output circuit. As a result, even when a potential at the ground wiring line is floated, a substantial decrease of a potential difference between the ground wiring line and the gate of the low-level outputting MOS transistor can be prevented. Also, a signal having a sufficiently high level can be supplied to a gate of a low-level outputting output MOS transistor. As a consequence, delays in the switching operation of the output MOS transistor can be suppressed, and the output circuit can be operated at high speed.Type: GrantFiled: September 29, 1997Date of Patent: June 6, 2000Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Toshikazu Tachibana, Takeshi Sakai, Yoshinobu Nakagome
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Patent number: 5983358Abstract: A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.Type: GrantFiled: September 26, 1997Date of Patent: November 9, 1999Assignees: Hitachi, Ltd., Hitachi Ulsi Engineering Corp., Hitachi Device Engineering Co., Ltd.Inventors: Masashi Horiguchi, Shinichi Miyatake, Tathunori Mushya, Yasuhiro Kasama, Yoichi Matsuno, Yasushi Kawase, Yoshinobu Nakagome
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Patent number: 5854636Abstract: A semiconductor integrated circuit having a two-dimensional array (MAR) and a parallel data transfer circuit (TRC) for transferring from the array data read out in parallel through data lines, in parallel to a processing circuit group (PE) by selecting the word lines of the two-dimensional memory array. The processing circuit group executing processing operations in parallel by using the data transferred from the parallel data transfer circuit. Each of the processing circuits having access to a plurality of series word lines and the data lines of the two-dimensional array through the parallel data transfer circuits. The arrangement of the parallel data transfer circuits allowing for an overlap range wherein data from each of the data lines of the memory array is available to more than one of the parallel data transfer circuits.Type: GrantFiled: September 16, 1997Date of Patent: December 29, 1998Assignee: Hitachi, Ltd.Inventors: Takao Watanabe, Yoshinobu Nakagome, Kazuo Ishikura, Tetsuya Nakagawa, Atsushi Kiuchi
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Patent number: 5835417Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.Type: GrantFiled: April 1, 1997Date of Patent: November 10, 1998Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Takao Watanabe, Yoshinobu Nakagome
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Patent number: 5677880Abstract: In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.Type: GrantFiled: March 21, 1995Date of Patent: October 14, 1997Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorporationInventors: Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Yoshinobu Nakagome, Hitoshi Tanaka, Kiyoo Itoh
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Patent number: 5657273Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The device is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished. The device is also capable of processing data on once-activated word lines successively thereby reducing the number of times each word line is driven so that the power consumption is reduced.Type: GrantFiled: November 15, 1995Date of Patent: August 12, 1997Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Takao Watanabe, Yoshinobu Nakagome
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Patent number: 5600163Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.Type: GrantFiled: August 16, 1994Date of Patent: February 4, 1997Assignee: Hitachi, Ltd.Inventors: Kazuo Yano, Tomoyuki Ishii, Takashi Hashimoto, Koichi Seki, Masakazu Aoki, Takeshi Sakata, Yoshinobu Nakagome, Kan Takeuchi
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Patent number: 5568083Abstract: The semiconductor integrated circuit device incorporates a power supply circuit which forms an operation voltage that matches the operation speed of the internal circuit. Since the operation voltage is set in accordance with the operation speed required of the internal circuit, the internal circuit can be operated with a minimum required voltage even when there are process variations and temperature changes. In other words, a rational power supply is realized.Type: GrantFiled: June 22, 1994Date of Patent: October 22, 1996Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.Inventors: Akira Uchiyama, Ryuji Shibata, Yoshinobu Nakagome, Masaharu Kubo
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Patent number: 5555215Abstract: The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.Type: GrantFiled: October 5, 1995Date of Patent: September 10, 1996Assignees: Hitachi, Ltd, Hitachi ULSI Engineering CorporationInventors: Yoshinobu Nakagome, Kiyoo Itoh, Hitoshi Tanaka, Yasushi Watanabe, Eiji Kume, Masanori Isoda, Eiji Yamasaki, Tatsumi Uchigiri
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Patent number: 5539692Abstract: A semiconductor chip is provided with a function selection circuit for selecting memory functions according to the information stored in nonvolatile memory elements is sealed in a package, and the memory functions are set finally by writing the nonvolatile memory element in that state or in a state in which the semiconductor chip is mounted on a board. By setting the type of a semiconductor memory according to the above procedure, the process from the wafer process up to the assembling step can be made common, and hence the mass-productibity and the production control can be facilitated. Semiconductor memories having memory functions conforming to user specifications can be provided in a short time.Type: GrantFiled: February 3, 1994Date of Patent: July 23, 1996Assignee: Hitachi, Ltd.Inventors: Kazuhiko Kajigaya, Masashi Horiguchi, Yoshinobu Nakagome, Ryoichi Hori, Tetsuro Matsumoto, Masaharu Kubo