Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A semiconductor memory device, comprising a fuse circuit which indicates a defective portion in a row direction, and also indicates the defective portion in a column direction, and a control circuit which switches data buses to avoid the defective portion indicated in the column direction by the fuse circuit when the defective portion indicated in the row direction by the fuse circuit corresponds to a row address that is input to the semiconductor memory device.

Abstract: An electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs. The electronic circuit apparatus includes at least one impedance circuit arranged between the bus and at least one of the stubs, and each impedance circuit has a high-pass filter characteristic. Therefore, ringing is suppressed, attenuation in the high-frequency components of a transmission signal is prevented, the definition of the signal is maintained, and transmission frequency and speed are both improved.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: A semiconductor device connected to at least one semiconductor device of the same type. The semiconductor device includes first pins, provided on a first side of the semiconductor device, for receiving signals commonly used with the at least one semiconductor device, and second pins, provided on a second side of the semiconductor device substantially perpendicular to the first side, for being connected to signal lines which are not connected to the at least one semiconductor device.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: The asynchronous data burst transfer circuit includes a data burst transfer oscillation circuit which outputs n strobe signals of mutually different phases, plural parallel-serial conversion circuits which convert n-bit parallel signals into serial signals, and plural serial-parallel conversion circuits which convert serial signals into n-bit parallel signals. The parallel-serial conversion circuits convert every n-bit parallel signals of data read from a memory into serial signals based on the strobe signals, and transfer the serial signals. The serial-parallel conversion circuits convert the received serial signals into n-bit parallel signals based on the strobe signals, thereby obtaining the parallel signals as the original data.

Abstract: Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock.

Abstract: A phase comparator compares the phases of first and second signals with each other. The phase comparator has a first control circuit, a second control circuit, and a phase comparator unit. The first control circuit divides the frequency of the first signal by n in response to a third signal where n is an integer equal to or larger than 2. The second control circuit divides the frequency of the second signal by n in response to the third signal. The phase comparator unit compares the phases of signals provided by the first and second control circuits with each other. The phase comparator unit is capable of correctly comparing the phases of even high-speed signals with each other, and therefore, is applicable to a DLL circuit that operates on high-speed clock signals.

Abstract: A semiconductor device including a plurality of blocks, each individual block of the plurality of blocks being capable of carrying out different types of internal operations, one internal operation at a time, and each internal operation lasting one cycle. A control unit configured to successively select one individual block after another from said plurality of blocks during each cycle is provided. The device is further configured upon selection of one individual block by the control unit, to execute the different types of internal operations one after another in a predetermined order and carry out the different types of internal operations in the one individual selected block in a pipe-line operation.

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state.

Abstract: A circuit includes a first phase-adjustment circuit adjusting phases of rising edges and falling edges of an original signal, and a phase-delay circuit receiving a phase-adjusted signal from said first phase-adjustment circuit and generating a delay signal by delaying said phase-adjusted signal by a predetermined phase amount. The circuit further includes a phase-comparison circuit comparing phases of edges between said phase-adjusted signal and said delay signal so as to control said first phase-adjustment circuit such that said phases of edges satisfy a predetermined phase relation.

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

Abstract: A signal-transfer system for transferring a signal via a line having no anti-signal-reflection resistor. The signal-transfer system includes a line having an equalized characteristic impedance Z.sub.0, and an output circuit having an output turn-on resistance Z.sub.0 /2 and outputting to the line a signal which has a voltage difference between a high level and a low level smaller than about 1 V.

Abstract: An interface circuit is constructed such that, when a switching in a potential level on a bus connected to semiconductor devices and transmitting data and control information is detected, the bus is controlled to be connected to one of predetermined potentials for a predetermined period of time, in correspondence with a direction in which the switching has occurred.