Abstract: A controlled delay circuit having a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A memory system using at least one DRAM chip and equipped with an interface for transferring input/output data in a packet format includes a plurality of banks within each of the at least one DRAM chip. The memory system further includes a control circuit for accessing a bank for data transfer of a given packet when the bank is different from a previous bank accessed for an immediately preceding packet, and for waiting for an operation to complete in the bank when the bank is the same as the previous bank.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state.

Abstract: A semiconductor device with a fuse is formed on a semiconductor substrate having a base semiconductor substrate and an epitaxial semiconductor layer formed thereon and defining a major surface of the semiconductor substrate. An isolation region is formed in the epitaxial semiconductor so as to completely surround and electrically isolate a selected region of the epitaxial layer on which the narrow, blowable portion of the fuse is disposed. A field oxide layer and an insulating layer are formed, in turn, over the fuse and on the main surface of the semiconductor layer and a passivation layer is formed on the insulating layer having an opening therein defined by interior sidewalls of the passivation layer which surround the selected region and which are disposed interiorally of the isolation region, and through which first opening a corresponding service of the insulating layer is exposed.

Abstract: An electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs. The electronic circuit apparatus includes at least one impedance circuit arranged between the bus and at least one of the stubs, and each impedance circuit has a high-pass filter characteristic. Therefore, ringing is suppressed, attenuation in the high-frequency components of a transmission signal is prevented, the definition of the signal is maintained, and transmission frequency and speed are both improved.

Abstract: An input buffer circuit includes a first amplifier causing a first change in an output signal by detecting a rising edge of an input signal, a second amplifier causing a second change in the output signal by detecting a falling edge of the input signal, and a feedback path feeding back the output signal as a feedback signal to the first amplifier and the second amplifier. The feedback signal controls the second amplifier such that a timing of the first change only depends on the first amplifier, and controls the first amplifier such that a timing of the second change only depends on the second amplifier.

Abstract: A semiconductor memory device includes a plurality of bit lines, first sense amplifiers each connected to a corresponding one of the plurality of bit lines, and a first data bus laid out in parallel to the plurality of bit lines and connected to the plurality of bit lines via gates and the first sense amplifiers. The semiconductor memory device further includes column-selection lines laid out perpendicularly to the plurality of bit lines to open at least one of the gates to connect the first data bus to the plurality of bit lines.

Abstract: An input buffer circuit includes a first amplifier causing a first change in an output signal by detecting a rising edge of an input signal, a second amplifier causing a second change in the output signal by detecting a falling edge of the input signal, and a feedback path feeding back the output signal as a feedback signal to the first amplifier and the second amplifier. The feedback signal controls the second amplifier such that a timing of the first change only depends on the first amplifier, and controls the first amplifier such that a timing of the second change only depends on the second amplifier.

Abstract: A transmission-line-voltage control circuit for controlling a level of a transmission line is disclosed. A signal of a first level indicating a logic high and a signal of a second level indicating a logic low are supplied to the transmission line. The transmission-line voltage control circuit includes a circuit connected to the transmission line. This circuit reduces, after the signal of the first level is supplied to the transmission line, the level of the transmission line to a third level which indicates the logic high and is less than the first level. And also the circuit increases, after the signal of the second level is supplied to the transmission line, the level of the transmission line to a fourth level which indicates the logic low and is higher than the second level.

Abstract: The semiconductor memory device of the present invention relates to an SRAM, is object to secure a saturation drain current of a driver transistor large enough for a saturation drain current of a transfer transistor while keeping the area occupied by a memory cell within a predetermined range, and has a memory cell comprising a strip-shaped word line which includes a gate electrode of a first transistor, extends in a definite direction on a semiconductor substrate, and bends diagonally to the definite direction and widens at a first transistor region; an active region which has source/drain regions of the first transistor and intersects the word line which is formed between the source/drain regions.

Abstract: A semiconductor integrated circuit includes a plurality of data buses, and emitter-follower circuits arranged in the data buses. Read parts, which are coupled to the emitter-follower circuits, read data transferred via the data buses via the emitter-follower circuits. A test part, which is coupled to the emitter-follower circuits, determines, in a test mode, whether or not the data transferred via the data buses have an error and outputs a test output signal to one of the data buses. The output test signal has a potential level higher than that of the data transferred via the data buses in a normal mode.

Abstract: This invention provides an apparatus in which a time difference between an eternal clock signal and an internal clock signal is eliminated, and in which a high operation speed even at a high operation frequency is accomplished without causing erroneous circuit operations. A semiconductor integrated circuit device is equipped with a signal generator for generating an internal clock signal for determining an operation timing of an internal circuit from an external clock signal. The semiconductor integrated circuit device includes a delay unit for bringing an edge of the external clock signal into conformity with the edge of the internal clock signal by delaying the output of the signal generator by the time obtained by subtracting a time corresponding to a circuit delay of the signal generator from a time corresponding to some integral multiple of a 1/2 cycle of the external clock signal.

Abstract: A semiconductor memory device, includes a memory cell array, a row decoder connected to the memory cell array by a plurality of word lines for selecting a word line in response to a first address signal supplied thereto, a column decoder connected to the memory cell array by a plurality of bit lines for selecting a bit line in response to a second address signal supplied thereto, and a data discrimination unit connected to the column decoder by a common data bus for producing an output data signal indicative of the data stored in the addressed memory cell. The column decoder includes a plurality of sense amplifiers each connected to a corresponding bit line for selecting an addressed bit line. The plurality of sense amplifiers are connected to a common data bus for carrying data stored in the addressed memory cell. A plurality of switching devices are provided in correspondence to the plurality of sense amplifiers for selectively transferring the data detected by the sense amplifier to the common data bus.

Abstract: A semiconductor memory device enabling change of the output organization has a plurality of memory cell array portions each having a plurality of memory cells for storing data, a plurality of data buses for transferring data, a plurality of sense amplifiers for sensing data of a selected memory cell of the memory cell array portions, and a plurality of output gates connected to the sense amplifiers. At least two of the sense amplifiers are connected to each of the memory cell array portions through the data buses, respectively. The selection of the sense amplifiers is controlled to be activated or deactivated by control signals, to thereby change the output organization. Therefore, a delay in data transmission can be eliminated, and a high speed operation can be realized.

Abstract: A level conversion circuit includes a first pMOS transistor having a source connected to a first power supply line, a gate receiving a first input signal, and a drain, and a second pMOS transistor having a source connected to the first power supply line, a gate receiving a second input signal, and a drain. A first nMOS transistor has a drain connected to a first output terminal and the drain of the first pMOS transistor, a gate, and a source. A first output signal is output via the first output terminal. A second nMOS transistor has a drain connected to a second output terminal, the drain of the second pMOS transistor and the gate of the first nMOS transistor, a gate connected to the drain of the first nMOS transistor, and a source. A second output signal is output via the second output terminal.

Abstract: A semiconductor integrated circuit includes an input circuit having a CMOS inverter and receiving an input signal. The input circuit has a threshold level which determines an output level of the input circuit with respect to the input signal. The integrated circuit includes an internal circuit receiving the input signal via the input circuit, the internal circuit receiving a first power supply voltage. A power source generates a second power supply voltage applied to the input circuit so that the second power supply voltage changes to cancel a change in the threshold level due to a temperature variation.

Abstract: A semiconductor integrated circuit includes a first P-channel MOS transistor and a second P-channel MOS transistor. The drain of the first P-channel MOS transistor is connected to the gate of the second P-channel MOS transistor. The second P-channel MOS transistor has a threshold voltage (a gate potential with respect to a source potential) greater than that of the first P-channel MOS transistor.

Abstract: A semiconductor memory device having a plurality of main memory cell arrays, a redundant memory cell array, a plurality of word lines provided in each of the main memory cell arrays and the redundant memory cell array, a plurality of bit lines, a plurality of common word lines extending throughout the plurality of main memory cell arrays and the redundant memory cell array, a row decoder for addressing a common word line in response to first address data, a plurality of word line switches for selectively connecting the common word line to a corresponding word line, and a column decoder supplied with second address data for addressing a bit line in a main memory cell. The column decoder has a controller for selectively disabling the addressing of bit line in response to incoming of a particular combination of the second address data to the column decoder.

Abstract: A semiconductor memory device of a bipolar-transistor type including a memory cell array, a redundancy array, a defective address memory circuit for storing a defective address and a comparing circuit for comparing an input address with the defective address. The defective address memory circuit includes a plurality of information memory circuits. The information memory circuits include a plurality of diode stages for determining their output amplitudes. When an input address coincides with the defective address stored in the address memory circuit, the redundancy array is selected instead of the memory cell array.