Abstract: A multilayer wiring substrate which is high in connection reliability is provided through process steps of forming more than one opening, such as a via-hole in a dielectric layer laminated on a substrate, and then applying uniform copper plating to a surface portion of the dielectric layer including the opening to thereby form a wiring layer. An electroless copper plating solution with at least one of mandelonitrile and triethyltetramine mixed therein is used to perform the intended electroless copper plating. An alternative process makes use of a electroless copper plating solution with chosen additive agents or “admixtures” containing at least one of mandelonitrile and triethyltetramine plus eriochrome black T along with at least one of 2,2′-bipyridyl, 1,10-phenanthroline, and 2,9-dimethyl-1,10-phenanthroline.

Abstract: An electroless copper plating solution using glyoxylic acid as a reducing agent, which is small in the reacting quantity of Cannizzaro reaction, does not largely cause precipitation of the salt accumulated in the electroless copper plating solution by the plating reaction and Cannizzaro reaction, and can be used stably over a long period of time. The electroless copper plating solution comprises copper ion, a complexing agent for copper ion, a reducing agent for copper ion and a pH adjusting agent, wherein the reducing agent for copper ion is glyoxylic acid or a salt thereof, the pH adjusting agent is potassium hydroxide and the electroless copper plating solution contains at least one member selected from metasilicic acid, metasilicic acid salt, germanium dioxide, germanic acid salt, phosphoric acid, phosphoric acid salt, vanadic acid, vanadic acid salt, stannic acid and stannic acid salt in an amount of 0.0001 mol/L or more.

Abstract: A voltage reference generation circuit is disclosed including a voltage reference generating stage and a voltage reference output stage, in which a depletion-mode MOS transistor and an enhancement-mode MOS transistor are connected in series, and the junction formed between these MOS transistors serves as an output terminal for outputting a voltage to be input to the voltage reference output stage. In the output stage, two enhancement-mode MOS transistors having the same channel dopant profile are connected in series between a power source and the ground, the gate of one MOS transistor is connected to the output terminal of the generating stage, the gate and drain of the other MOS transistor are interconnected, and the junction formed between these MOS transistors serves as an output terminal for a voltage reference.

Abstract: A semiconductor apparatus incorporating MOS transistors with reduced narrow or reverse narrow channel effect and a method for forming the semiconductor apparatus are disclosed. The semiconductor apparatus includes at least a field oxide layer for device isolation formed on a semiconductor substrate, a channel stopper region formed under the field oxide layer, and a MOS transistor of a first conductivity type electrically isolated by the field oxide layer and channel stopper region, in which the MOS transistor includes an impurity region for controlling narrow effect formed in the vicinity of both ends of a channel region in the direction of channel width, and a high concentration impurity region formed having an impurity concentration approximately equal to that of the channel stopper region at the location deeper than the channel stopper region.

Abstract: A semiconductor device is provided comprising several device components formed in the same substrate, such as a P-substrate having an offset Nch transistor including N-type source and drain each formed in a P-well spatially separated from one another, and the drain surrounded by a low concentration N-type diffusion layer; an offset Pch transistor including P-type source and drain each formed in an N-well spatially separated from one another, and the drain surrounded by a low concentration P-type diffusion layer; a triple well including a deep N-well, and a P-type IP well formed therein; a normal N-well for forming a Pch MOS transistor; and a normal P-well for forming an Nch MOS transistor; in which simultaneously formed are the low concentration N-type diffusion layer, N-well and normal N-well; the P-well and normal P-well; and the low concentration P-type diffusion layer and IP well.

Abstract: A voltage reference generation circuit is disclosed including a voltage reference generating stage and a voltage reference output stage, in which a depletion-mode MOS transistor and an enhancement-mode MOS transistor are connected in series, and the junction formed between these MOS transistors serves as an output terminal for outputting a voltage to be input to the voltage reference output stage. In the output stage, two enhancement-mode MOS transistors having the same channel dopant profile are connected in series between a power source and the ground, the gate of one MOS transistor is connected to the output terminal of the generating stage, the gate and drain of the other MOS transistor are interconnected, and the junction formed between these MOS transistors serves as an output terminal for a voltage reference.

Abstract: A voltage reference generation circuit is disclosed including a voltage reference generating stage and a voltage reference output stage, in which a depletion-mode MOS transistor and an enhancement-mode MOS transistor are connected in series, and the junction formed between these MOS transistors serves as an output terminal for outputting a voltage to be input to the voltage reference output stage. In the output stage, two enhancement-mode MOS transistors having the same channel dopant profile are connected in series between a power source and the ground, the gate of one MOS transistor is connected to the output terminal of the generating stage, the gate and drain of the other MOS transistor are interconnected, and the junction formed between these MOS transistors serves as an output terminal for a voltage reference.

Abstract: This invention provides an electroless copper plating solution using glyoxylic acid as a reducing agent, which is small in the reacting quantity of Cannizzaro reaction, does not largely cause precipitation of the salt accumulated in the electroless copper plating solution by the plating reaction and Cannizzaro reaction, and can be used stably over a long period of time.

Abstract: A resistance element of a semiconductor device includes a first resistance pattern and a second resistance pattern formed adjacent to the first resistance pattern at a lower level, wherein the second resistance pattern is defined by the first resistance pattern in a self-aligned relationship and connected to the first resistance pattern in series.

Abstract: Providing a multilayer wiring substrate high in connection reliability through process steps of forming more than one opening such as a via-hole in a dielectric layer laminated on a substrate and then applying uniform copper plating to a surface portion of the dielectric layer including the opening to thereby form a wiring layer.

Abstract: A voltage reference generation circuit is disclosed including a voltage reference generating stage and a voltage reference output stage, in which a depletion-mode MOS transistor and an enhancement-mode MOS transistor are connected in series, and the junction formed between these MOS transistors serves as an output terminal for outputting a voltage to be input to the voltage reference output stage. In the output stage, two enhancement-mode MOS transistors having the same channel dopant profile are connected in series between a power source and the ground, the gate of one MOS transistor is connected to the output terminal of the generating stage, the gate and drain of the other MOS transistor are interconnected, and the junction formed between these MOS transistors serves as an output terminal for a voltage reference.

Abstract: Abnormal flows in an extractor are simulated, with a flow divider model and a flow merger model being introduced. Overflow state, entrainment occurrence state, and reflux state in the extractor are simulated. Moreover, abnormal flows under a variety of conditions are simulated efficiently by using object-oriented software as the simulation program.

Abstract: A molded capsule having a capsule membrane which contains a Process Whey Protein together with at least one selected from the group consisting of scleroproteins, derived proteins and mucopolysaccharides. The capsule membrane may contain a plasticizer. The molded capsule has high membrane strength, exhibits stability even at high temperatures and high humidity, and is highly digestible. The molded capsule is prepared by using a die rolls encapsulating machine.

Abstract: An apparatus prints the necessary attribute on an identity tag immediately before a cut wiring cable is inserted thereinto, and automatically attaching the printed identity tag to the wiring cable. An identity tag attaching apparatus attaches an identity tag which represents the attribute of a cable to the cable.

Abstract: A method for manufacturing a Bi-CMOS device by preparing both of bipolar and MOS standard cells in a library is provided. A substrate of a first conductivity type is provided and a plurality of buried layers of a second conductivity type are formed on selected locations of the substrate. Then an epitaxial layer of the first conductivity type is formed on the substrate covering the buried layers. Then a plurality of wells of the second conductivity type are formed in the epitaxial layer such that each of the wells extends through the epitaxial layer from the top surface to at least a portion of the corresponding buried layer to thereby define a plurality of electrically isolated islands in the epitaxial layer. Then a bipolar transistor is formed in at least one of the islands with a MOS transistor formed in at least another of the islands.