Patents by Inventor Yoshio Kawashima

Yoshio Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8481990
    Abstract: A variable resistance nonvolatile memory element capable of suppressing a variation in resistance values is provided.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: July 9, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshio Kawashima, Takumi Mikawa, Yukio Hayakawa
  • Patent number: 8471235
    Abstract: A nonvolatile memory element includes a substrate; a lower electrode layer and a resistive layer sequentially formed on the substrate; a resistance variable layer formed on the resistive layer; a wire layer formed above the lower electrode layer; an interlayer insulating layer disposed between the substrate and the wire layer and covering at least the lower electrode layer and the resistive layer, the interlayer insulating layer being provided with a contact hole extending from the wire layer to the resistance variable layer; and an upper electrode layer formed inside the contact hole such that the upper electrode layer is connected to the resistance variable layer and to the wire layer; resistance values of the resistance variable layer changing reversibly in response to electric pulses applied between the lower electrode layer and the upper electrode layer.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshio Kawashima, Takumi Mikawa, Zhiqiang Wei, Atsushi Himeno
  • Publication number: 20130149815
    Abstract: A method of manufacturing a nonvolatile memory element includes: forming a first conductive film above a substrate; forming, above the first conductive film, a first metal oxide layer and a second metal oxide layer having different degrees of oxygen deficiency and a second conductive film; forming a second electrode by patterning the second conductive film; forming a variable resistance layer by patterning the first metal oxide layer and the second metal oxide layer; removing a side portion of the variable resistance layer in a surface parallel to a main surface of the substrate to a position that is further inward than an edge of the second electrode; and forming a first electrode by patterning the first conductive film after or during the removing.
    Type: Application
    Filed: September 10, 2012
    Publication date: June 13, 2013
    Inventors: Hideaki Murase, Takumi Mikawa, Yoshio Kawashima, Atsushi Himeno
  • Publication number: 20130140515
    Abstract: A method of manufacturing a nonvolatile memory element, the method including: forming a first lower electrode layer, a current steering layer, and a first upper electrode layer; forming a second lower electrode layer, a variable resistance layer, and a second upper electrode layer on the first upper electrode layer; patterning the second upper electrode layer, the variable resistance layer, and the lower electrode layer; patterning the first upper electrode layer, the current steering layer, and first lower electrode layer to form a current steering element, using the second lower electrode layer as a mask by use of etching which is performed on the second lower electrode layer at an etching rate lower than at least etching rates at which the second upper electrode layer and the variable resistance layer are etched; and forming a variable resistance element which has an area smaller than the area of the current steering element.
    Type: Application
    Filed: February 22, 2012
    Publication date: June 6, 2013
    Inventors: Yoshio Kawashima, Takumi Mikawa, Ichirou Takahashi
  • Patent number: 8445883
    Abstract: A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventors: Atsushi Himeno, Takumi Mikawa, Yoshio Kawashima
  • Publication number: 20130119344
    Abstract: A variable resistance nonvolatile storage element includes: a first electrode; a second electrode; and a variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the electrodes, wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide layer, a second transition metal oxide layer, and a third transition metal oxide layer in this order, the first transition metal oxide layer having a composition expressed as MOx (where M is a transition metal and O is oxygen), the second transition metal oxide layer having a composition expressed as MOy (where x>y), and the third transition metal oxide layer having a composition expressed as MOz (where y>z).
    Type: Application
    Filed: October 6, 2011
    Publication date: May 16, 2013
    Inventors: Takumi Mikawa, Yukio Hayakawa, Takeki Ninomiya, Yoshio Kawashima, Shinichi Yoneda
  • Publication number: 20130112936
    Abstract: A variable resistance element including: a first electrode; a second electrode; and a variable resistance layer having a resistance value which reversibly changes according to electrical signals applied, wherein the variable resistance layer includes a first variable resistance layer comprising a first oxygen-deficient transition metal oxide, and a second variable resistance layer comprising a second transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first transition metal oxide layer, the second electrode has a single needle-shaped part at the interface with the second variable resistance layer, and the second variable resistance layer is interposed between the first variable resistance layer and the second electrode, is in contact with the first variable resistance layer and the second electrode, and covers the needle-shaped part.
    Type: Application
    Filed: January 18, 2012
    Publication date: May 9, 2013
    Applicant: Panasonic Corporation
    Inventors: Zhiqiang WEI, Takeshi Takagi, Satoru Mitani, Yoshio Kawashima, Ichirou Takahashi
  • Patent number: 8437173
    Abstract: A nonvolatile memory element which can be initialized at low voltage includes a variable resistance layer (116) located between a lower electrode (105) and an upper electrode (107) and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer (116) includes at least two layers: a first variable resistance layer (1161) including a first transition metal oxide (116b); and a second variable resistance layer (1162) including a second transition metal oxide (116a) and a third transition metal oxide (116c). The second transition metal oxide (116a) has an oxygen deficiency higher than either oxygen deficiency of the first transition metal oxide (116b) or the third transition metal oxide (116c), and the second transition metal oxide (116a) and the third transition metal oxide (116c) are in contact with the first variable resistance layer (1161).
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: May 7, 2013
    Assignee: Panasonic Corporation
    Inventors: Yukio Hayakawa, Takumi Mikawa, Yoshio Kawashima, Takeki Ninomiya
  • Patent number: 8426836
    Abstract: There are provided a resistance variable nonvolatile memory device which changes its resistance stably at low voltages and is suitable for a miniaturized configuration, and a manufacturing method thereof. The nonvolatile memory device comprises: a substrate (100); a first electrode (101); an interlayer insulating layer (102); a memory cell hole (103) formed in the interlayer insulating layer; a first resistance variable layer (104a) formed in at least a bottom portion of the memory cell hole and connected to the first electrode; a second resistance variable layer (104b) formed inside the memory cell hole (103) and located on the first resistance variable layer (104a); and a second electrode (105); the first resistance variable layer (104a) and the second resistance variable layer (104b) respectively comprising metal oxides of the same kind; and the first resistance variable layer (104a) having a higher oxygen content than the second resistance variable layer (104b).
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: April 23, 2013
    Assignee: Panasonic Corporation
    Inventors: Takumi Mikawa, Yoshio Kawashima, Atsushi Himeno
  • Publication number: 20130092893
    Abstract: The method includes: forming a lower electrode layer above a substrate; forming a variable resistance layer on the lower electrode layer; forming an upper electrode layer on the variable resistance layer; forming a hard mask layer on the upper electrode layer; forming a photoresist mask on the hard mask layer; forming a hard mask by performing etching on the hard mask layer using the photoresist mask; and forming a nonvolatile memory element by performing etching on the upper electrode layer, the variable resistance layer, and the lower electrode layer, using the hard mask. In the forming of a photoresist mask, the photoresist mask is formed to have corner portions which recede toward the center portion in planar view.
    Type: Application
    Filed: June 30, 2011
    Publication date: April 18, 2013
    Inventors: Yoshio Kawashima, Takumi Mikawa
  • Patent number: 8394669
    Abstract: A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: March 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Koji Arita, Takumi Mikawa, Atsushi Himeno, Yoshio Kawashima, Kenji Tominaga
  • Patent number: 8389972
    Abstract: To realize miniaturization and increased capacity of memories by lowering break voltage for causing resistance change and suppressing variation in break voltage. The nonvolatile memory device (10) in the present invention includes: a lower electrode (105) formed above a substrate (100); a first variable resistance layer (106a) formed above the lower electrode (105) and comprising a transitional metal oxide; a second variable resistance layer (106b) formed above the first variable resistance layer (106a) and comprising a transitional metal oxide having higher oxygen content than the transitional metal oxide of the first variable resistance layer (106a); and an upper electrode (107) formed above the second variable resistance layer (106b), wherein a step (106ax) is formed in an interface between the first variable is resistance layer (106a) and the second variable resistance layer (106b).
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: March 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Takumi Mikawa, Yoshio Kawashima
  • Patent number: 8389990
    Abstract: A nonvolatile semiconductor memory device of the present invention includes a substrate (1), first wires (2), memory cells each including a resistance variable element (5) and a portion of a diode element (6), second wires (11) which respectively cross the first wires (2) to be perpendicular to the first wires (2) and each of which contains a remaining portion of the diode element (6), and upper wires (13) formed via an interlayer insulating layer (12), respectively, and the first wires (2) are connected to the upper wires (13) via first contacts (14), respectively, and the second wires (11) are connected to the upper wires (13) via second contacts (15), respectively.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: March 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Takumi Mikawa, Yoshio Kawashima, Ryoko Miyanaga
  • Publication number: 20130015423
    Abstract: Provided is a method for manufacturing a variable resistance nonvolatile semiconductor memory element, and a nonvolatile semiconductor memory element which make it possible to operate at a low voltage and high speed when initial breakdown is caused, and exhibit favorable diode element characteristics. The method for manufacturing the nonvolatile semiconductor memory element includes, after forming a top electrode of a variable resistance element and at least before forming a top electrode of an MSM diode element, oxidizing to insulate a portion of a variable resistance film in a region around an end face of a variable resistance layer.
    Type: Application
    Filed: November 18, 2011
    Publication date: January 17, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Takumi Mikawa, Yukio Hayakawa, Yoshio Kawashima, Takeki Ninomiya
  • Patent number: 8344345
    Abstract: A first wire layer (19) including first memory wires (12) is connected to a second wire layer (20) including second memory wires (17) via first contacts (21) penetrating a first interlayer insulating layer (13). The first wire layer (13) is connected to and led out to upper wires (22) via second contacts (26) connected to the second wire layer (20) and penetrating the second interlayer insulating layer (18). The first contacts (21) penetrate semiconductor layer (17b) or insulator layer (17c) of the second wire layer (20).
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Takumi Mikawa, Yoshio Kawashima, Ryoko Miyanaga
  • Publication number: 20120298945
    Abstract: A nonvolatile semiconductor memory device of the present invention includes a substrate (1), first wires (2), memory cells each including a resistance variable element (5) and a portion of a diode element (6), second wires (11) which respectively cross the first wires (2) to be perpendicular to the first wires (2) and each of which contains a remaining portion of the diode element (6), and upper wires (13) formed via an interlayer insulating layer (12), respectively, and the first wires (2) are connected to the upper wires (13) via first contacts (14), respectively, and the second wires (11) are connected to the upper wires (13) via second contacts (15), respectively.
    Type: Application
    Filed: May 31, 2012
    Publication date: November 29, 2012
    Applicant: Panasonic Corporation
    Inventors: Takumi MIKAWA, Yoshio Kawashima, Ryoko Miyanaga
  • Publication number: 20120252184
    Abstract: A variable resistance element comprises, when M is a transition metal element, O is oxygen, and x and y are positive numbers satisfying y>x; a lower electrode; a first oxide layer formed on the lower electrode and comprising MOx when a content ratio of O with respect to M is x; a second oxide layer formed on the first oxide layer and comprising MOy when a content ratio of O with respect to M is y; an upper electrode formed on the second oxide layer; a protective layer formed on the upper electrode and comprising an electrically conductive material having a composition different from a composition of the upper electrode; an interlayer insulating layer formed to cover the protective layer; and an upper contact plug formed inside an upper contact hole penetrating the interlayer insulating layer.
    Type: Application
    Filed: December 14, 2010
    Publication date: October 4, 2012
    Inventors: Takeki Ninomiya, Yoshio Kawashima, Yukio Hayakawa, Takumi Mikawa
  • Publication number: 20120238055
    Abstract: An object of the present invention is to provide a method for manufacturing a variable resistance nonvolatile semiconductor memory element which can operate at a low voltage and high speed when initial breakdown is caused, and inhibit oxidization of a contact plug. The method for manufacturing the variable resistance nonvolatile semiconductor memory element, which includes a bottom electrode, a variable resistance layer, and a top electrode which are formed above a contact plug, includes oxidizing to insulate an end portion of the variable resistance layer prior to forming a bottom electrode by patterning a first conductive film.
    Type: Application
    Filed: November 10, 2011
    Publication date: September 20, 2012
    Inventors: Takumi Mikawa, Yukio Hayakawa, Takeki Ninomiya, Yoshio Kawashima
  • Patent number: 8253136
    Abstract: A nonvolatile semiconductor memory device of the present invention includes a substrate (1), first wires (2), memory cells each including a resistance variable element (5) and a portion of a diode element (6), second wires (11) which respectively cross the first wires (2) to be perpendicular to the first wires (2) and each of which contains a remaining portion of the diode element (6), and upper wires (13) formed via an interlayer insulating layer (12), respectively, and the first wires (2) are connected to the upper wires (13) via first contacts (14), respectively, and the second wires (11) are connected to the upper wires (13) via second contacts (15), respectively.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: August 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Takumi Mikawa, Yoshio Kawashima, Ryoko Miyanaga
  • Patent number: 8242479
    Abstract: A nonvolatile memory device includes via holes (12) formed at cross sections where first wires (11) cross second wires (14), respectively, and current control elements (13) each including a current control layer (13b), a first electrode layer (13a) and a second electrode layer (13c) such that the current control layer (13b) is sandwiched between the first electrode layer (13a) and the second electrode layer (13c), in which resistance variable elements (15) are provided inside the via holes (12), respectively, the first electrode layer (13a) is disposed so as to cover the via hole (12), the current control layer (13b) is disposed so as to cover the first electrode layer (13a), the second electrode layer (13c) is disposed on the current control layer (13b), a wire layer (14a) of the second wire is disposed on the second electrode layer (13c), and the second wires (14) each includes the current control layer (13b), the second electrode layer (13c) and the wire layer (14a) of the second wire.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: August 14, 2012
    Assignee: Panasonic Corporation
    Inventors: Yoshio Kawashima, Takumi Mikawa, Ryoko Miyanaga, Takeshi Takagi