Abstract: A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

Abstract: Memory elements (3) arranged in matrix in a memory apparatus (21), each includes a resistance variable element (1) which changes an electrical resistance value in response to an applied electrical pulse having a positive polarity or a negative polarity and maintains the changed electrical resistance value, and a current suppressing element (2) for suppressing a current flowing when the electrical pulse is applied to the resistance variable element. The current suppressing element includes a first electrode, a second electrode, and a current suppressing layer provided between the first electrode and the second electrode, and the current suppressing layer comprises SiNx (x: positive actual number).

Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transi

Abstract: A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed.

Abstract: A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.

Abstract: A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed.

Abstract: A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.

Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transi

Abstract: The present invention provides a magnetoresistive (MR) element that is excellent in MR ratio and thermal stability and includes at least one magnetic layer including a ferromagnetic material M-X expressed by M100-aXa. Here, M is at least one selected from Fe, Co and Ni, X is expressed by X1bX2cX3d (X1 is at least one selected from Cu, Ru, Rh, Pd, Ag, Os, Ir, Pt and Au, X2 is at least one selected from Al, Sc, Ti, V, Cr, Mn, Ga, Ge, Y, Zr, Nb, Mo, Hf, Ta, W, Re, Zn and lanthanide series elements, and X3 is at least one selected from Si, B, C, N, O, P and S), and a, b, c and d satisfy 0.05?a?60, 0?b?60, 0?c?30, 0?d?20, and a=b+c+d.

Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transi

Abstract: A lid unit seals a container main body of a thin-plate supporting container which is conveyed while plural 300 mm-diameter semiconductor wafers are stored in the container. In a wafer retainer which supports the wafers stored in the container main body, the maximum amount of displacement is set in a range of 1.5 to 2.5 mm (ranges from 1/200 to 1/120 of the semiconductor wafer diameter), and proportionality is held between the amount of displacement and external force when the maximum amount of displacement ranges from 1.5 to 2.5 mm. In the states in which the wafer retainer is fitted in the container main body and force is not applied, the wafer retainer is arranged at a position in which the wafer retainer is not in contact with the semiconductor wafers stored in the container main body or at a position in which the wafer retainer is in slight contact with the semiconductor wafers.

Abstract: A magnetic memory of the present invention includes two or more memory layers and two or more tunnel layers that are stacked in the thickness direction of the layers. The two or more memory layers are connected electrically in series. A group of first layers includes at least one layer selected from the two or more memory layers. A group of second layers includes at least one layer selected from the two or more memory layers. A resistance change caused by magnetization reversal in the group of first layers differs from a resistance change caused by magnetization reversal in the group of second layers.

Abstract: The present invention provides a method for producing a magnetoresistive element including a tunnel insulating layer, and a first magnetic layer and a second magnetic layer that are laminated so as to sandwich the tunnel insulating layer, wherein a resistance value varies depending on a relative angle between magnetization directions of the first magnetic layer and the second magnetic layer.

Abstract: A magnetoresistive element includes a pair of ferromagnetic layers and a non-magnetic layer arranged between the ferromagnetic layers. At least one of the ferromagnetic layers has a composition expressed by (MxLy)100-zRz at the interface with the non-magnetic layer. The non-magnetic layer includes at least one element selected from the group consisting of B, C, N, O, and P. Here, M is FeaCobNic, L is at least one element selected from the group consisting of Pt, Pd, Ir, and Rh, R is an element that has a lower free energy to form a compound with the element of the non-magnetic layer that is at least one selected from the group consisting of B, C, N, O, and P than does any other element included in the composition as M or L, and a, b, c, x, y, and z satisfy a+b+c=100, a?30, x+y=100, 0<y?35, and 0.1?z?20. This element can provide a high MR ratio. A method for manufacturing a magnetoresistive element includes a first heat treatment process at 200° C. to 330° C.

Abstract: A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.

Abstract: The present invention provides a magnetoresistive (MR) element that is excellent in MR ratio and thermal stability and includes at least one magnetic layer including a ferromagnetic material M-X expressed by M100-aXa. Here, M is at least one selected from Fe, Co and Ni, X is expressed by X1bX2c,X3d (X1 is at least one selected from Cu, Ru, Rh, Pd, Ag, Os, Ir, Pt and Au, X2 is at least one selected from Al, Sc, Ti, V, Cr, Mn, Ga, Ge, Y, Zr, Nb, Mo, Hf, Ta, W, Re, Zn and lanthanide series elements, and X3 is at least one selected from Si, B, C, N, O, P and S), and a, b, c and d satisfy 0.05?a?60, 0?b?60, 0?c?30, 0?d?20, and a=b+c+d.

Abstract: A magnetoresistive element of the present invention includes a multilayer structure that includes a non-magnetic layer (3) and a pair of ferromagnetic layers (1, 2) stacked on both sides of the non-magnetic layer (3). A resistance value differs depending on a relative angle between the magnetization directions of the ferromagnetic layers (1, 2) at the interfaces with the non-magnetic layer (3). The composition of at least one of the ferromagnetic layers (1, 2) in a range of 2 nm from the interface with the non-magnetic layer (3) is expressed by (MxOy)1-zZz, where Z is at least one element selected from the group consisting of Ru, Os, Rh, Ir, Pd, Pt, Cu, Ag, and Au, M is at least one element selected from the group consisting of elements other than Z and O and includes a ferromagnetic metal, and x, y, and z satisfy 0.33<y/x<1.33, 0<x, 0<y, and 0?z?0.4. This magnetoresistive element can have excellent heat resistance and magnetoresistance characteristics.

Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transi

Abstract: A magnetoresistive element of the present invention includes a multilayer structure that includes a non-magnetic layer (3) and a pair of ferromagnetic layers (1, 2) stacked on both sides of the non-magnetic layer (3). A resistance value differs depending on a relative angle between the magnetization directions of the ferromagnetic layers (1, 2) at the interfaces with the non-magnetic layer (3). The composition of at least one of the ferromagnetic layers (1, 2) in a range of 2 nm from the interface with the non-magnetic layer (3) is expressed by (MxOy)1-zZz, where Z is at least one element selected from the group consisting of Ru, Os, Rh, Ir, Pd, Pt, Cu, Ag, and Au, M is at least one element selected from the group consisting of elements other than Z and O and includes a ferromagnetic metal, and x, y, and z satisfy 0.33<y/x<1.33, 0<x, 0<y, and 0≦z≦0.4. This magnetoresistive element can have excellent heat resistance and magnetoresistance characteristics.

Abstract: The present invention provides a method for producing a magnetoresistive element including a tunnel insulating layer, and a first magnetic layer and a second magnetic layer that are laminated so as to sandwich the tunnel insulating layer, wherein a resistance value varies depending on a relative angle between magnetization directions of the first magnetic layer and the second magnetic layer.