Patents by Inventor Yoshio Ozawa
Yoshio Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150030978Abstract: A magnetic toner for developing an electrostatic latent image of the present disclosure includes toner particles each having a toner core containing a binder resin and a magnetic powder, and a shell layer coating a surface of the toner core. The shell layer contains a unit derived from a monomer of a thermosetting resin and a unit derived from a thermoplastic resin. The thermosetting resin is one or more resins selected from the group of amino resins consisting of a melamine resin, a urea resin, and a glyoxal resin. The amount of iron eluted from the toner core (iron concentration in a filtrate) measured by a specified method is 10 mg/L or less.Type: ApplicationFiled: July 23, 2014Publication date: January 29, 2015Applicant: KYOCERA Document Solutions Inc.Inventors: Yoshio OZAWA, Toshiki TAKEMORI, Masanori SUGAHARA, Hiroaki MORIYAMA, Masashi TAMAGAKI
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Patent number: 8941088Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.Type: GrantFiled: September 27, 2013Date of Patent: January 27, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
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Publication number: 20150017582Abstract: An electrostatic latent image developing toner includes toner particles each including a toner core and a shell layer. The shell layer contains a resin including a unit derived from a monomer of a thermosetting resin and a unit derived from a thermoplastic resin. The thermosetting resin is one or more resins selected from the group of amino resins consisting of a melamine resin, a urea resin, and a glyoxal resin. When heat and pressure are applied to a toner layer formed on a polyester film under conditions of a temperature of 140° C. and a pressure of 7 MPa so that the toner particles are not superimposed, the toner particles of the toner layer are broken in a manner that a melt of a component of the toner core flows out from a plurality of points in an outer surface of the shell layer.Type: ApplicationFiled: July 7, 2014Publication date: January 15, 2015Applicant: KYOCERA DOCUMENT SOLUTIONS INC.Inventors: Yoshio OZAWA, Noriaki SAKAMOTO, Hiroaki MORIYAMA, Tomoyuki OGAWA, Takatoshi NOZAKI
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Publication number: 20150004540Abstract: An electrostatic latent image developing toner contains toner particles each including a toner core containing a binder resin, and a shell layer coating the surface of the tore core. The shell layer contains a unit derived from a monomer of a thermosetting resin, and a unit derived from a thermoplastic resin. The resin contained in the shell layer has a unit derived from one or more monomers of thermosetting resins selected from the group of amino resins consisting of a melamine resin, a urea resin, and a glyoxal resin.Type: ApplicationFiled: June 26, 2014Publication date: January 1, 2015Applicant: KYOCERA DOCUMENT SOLUTIONS INC.Inventors: Yoshio OZAWA, Naruo YABE, Masami TSUJIHIRO, Ryotaro KOMADA
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Publication number: 20150004537Abstract: The present disclosure relates to an electrostatic latent image developing toner containing a toner particle including a toner core containing a binder resin and a shell layer coating a surface of the toner core. The shell layer contains a unit derived from a monomer of a thermosetting resin, and a unit derived from a thermoplastic resin. The thermosetting resin is one or more resins selected from the group of amino resins consisting of a melamine resin, a urea resin, and a glyoxal resin. The toner particle contains fine particles in an interfacial portion between the toner core and the shell layer, and the fine particles have a charge property opposite to that of the toner, or have a volume resistivity lower than both a volume resistivity of the binder resin and a volume resistivity of the shell layer.Type: ApplicationFiled: June 26, 2014Publication date: January 1, 2015Applicant: KYOCERA Document Solutions Inc.Inventors: Yoshio OZAWA, Masami TSUJIHIRO, Toru TAKATSUNA, Ryotaro KOMADA
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Publication number: 20140374690Abstract: A semiconductor element includes a first electrode having at least one convex feature, a second electrode having a concave feature opposed to the convex feature, and a variable resistance layer including an element whose absolute value of standard reaction Gibbs energy for forming oxide is larger than the corresponding value of an element included in the first electrode, and being disposed between the convex feature and the concave feature or on the outer circumference of the convex feature of the first electrode.Type: ApplicationFiled: June 18, 2014Publication date: December 25, 2014Inventors: Junichi WADA, Yoshio OZAWA
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Publication number: 20140357032Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.Type: ApplicationFiled: August 15, 2014Publication date: December 4, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Yoshio OZAWA
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Publication number: 20140308789Abstract: According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.Type: ApplicationFiled: June 25, 2014Publication date: October 16, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tetsuya Kai, Yoshio Ozawa, Ryota Fujitsuka, Yoshitaka Tsunashima
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Publication number: 20140284546Abstract: According to one embodiment, a memory element includes: a first electrode layer; a second electrode layer; and a memory layer provided between the first electrode layer and the second electrode layer, and the memory layer including a plurality of first oxide layers in a second oxide layer, a resistivity of each of the plurality of first oxide layers being higher than a resistivity of the second oxide layer.Type: ApplicationFiled: September 10, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomotaka ARIGA, Junichi WADA, Kouji MATSUO, Noritake OOMACHI, Yoshio OZAWA
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Patent number: 8841183Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.Type: GrantFiled: March 10, 2011Date of Patent: September 23, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Yoshio Ozawa
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Publication number: 20140264227Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: ApplicationFiled: May 27, 2014Publication date: September 18, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Masahiro KIYOTOSHI, Akihito YAMAMOTO, Yoshio OZAWA, Fumitaka ARAI, Riichiro SHIROTA
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Publication number: 20140252453Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.Type: ApplicationFiled: May 22, 2014Publication date: September 11, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Masaaki HIGUCHI, Yoshio Ozawa, Katsuyuki Sekine, Ryota Fujitsuka
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Patent number: 8829593Abstract: A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.Type: GrantFiled: March 18, 2010Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Kensuke Takano, Masaaki Higuchi, Tetsuya Kai, Yoshio Ozawa
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Patent number: 8803221Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate; a tunnel insulating film on the substrate; a charge storage layer on the tunnel insulating film; a block insulating film on the charge storage layer; a first element isolation insulating film in an element isolation trench in the substrate, having a bottom surface lower than an interface between the substrate and the tunnel insulating film, and having a top surface lower than an interface between the charge storage layer and the block insulating film; a second element isolation insulating film on the first element isolation insulating film, protruding to a top surface of the block insulating film, in contact with a side surface of the block insulating film, and having a higher Si concentration than the block insulating film; and a control gate electrode on the block insulating film and on the second element isolation insulating film.Type: GrantFiled: September 13, 2011Date of Patent: August 12, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kai, Yoshio Ozawa
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Patent number: 8796757Abstract: According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.Type: GrantFiled: March 21, 2011Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kai, Yoshio Ozawa, Ryota Fujitsuka, Yoshitaka Tsunashima
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Patent number: 8766373Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: GrantFiled: July 19, 2011Date of Patent: July 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
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Patent number: 8759901Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.Type: GrantFiled: August 12, 2010Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Higuchi, Yoshio Ozawa, Katsuyuki Sekine, Ryota Fujitsuka
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Publication number: 20140120466Abstract: An electrostatic latent image developing toner includes toner base particles including a binder resin and an external additive attached to surfaces of the toner base particles. The external additive contains silica covered with a coating layer containing a nitrogen containing resin.Type: ApplicationFiled: October 24, 2013Publication date: May 1, 2014Applicant: KYOCERA DOCUMENT SOLUTIONS INC.Inventors: Masami TSUJIHIRO, Yoshio OZAWA
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Publication number: 20140087301Abstract: A carrier for electrostatic latent image developing is composed of carrier core containing a binder resin and magnetic material particles, and a shell layer that covers the carrier core. The binder has an acid value of at least a predetermined value, and contains a resin having a carboxyl group. The shell layer is composed of a resin selected from melamine resin and urea resin.Type: ApplicationFiled: September 25, 2013Publication date: March 27, 2014Applicant: KYOCERA Document Solutions Inc.Inventors: Masami Tujihiro, Yoshio Ozawa
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Patent number: 8674426Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked body, a semiconductor pillar and a charge storage layer. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The semiconductor pillar is buried in the stacked body, and extends in a stacking direction of the insulating films and the electrode films. The charge storage layer is provided between the electrode films and the semiconductor pillar. The electrode films are divided into a plurality of control gate electrodes. Each of the plurality of control gate electrodes faces the semiconductor pillar and sandwiches the charge storage layer with the semiconductor pillar.Type: GrantFiled: February 8, 2011Date of Patent: March 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Higuchi, Yoshio Ozawa