Abstract: A power storage cell includes a cell case and an electrode assembly. The cell case accommodates the electrode assembly. The cell case includes a case main body and a cover. The cover includes a first electrode terminal, an insulating member, an inversion plate, a cover main body, and a second electrode terminal. The cover main body electrically connects the inversion plate and the second electrode terminal to each other. The insulating member electrically insulates the first electrode terminal and the cover main body from each other. The inversion plate has a first surface. The first electrode terminal has a second surface. A groove group is formed in at least one of the first surface and the second surface.

Abstract: An LED unit which serves as illumination light source to be attached to lighting equipment, includes: a mounting board on which a light-emitting element, which emits light frontward, is provided; a support pad disposed behind the mounting board; and a case disposed so that the mounting board is sandwiched in a front-back direction by the case and the support pad. The support pad or the case includes insertion holes which are three or more openings into which securing components for securing the LED unit to the lighting equipment are inserted, and the three or more openings are disposed in such a way that, when a distance between two of the three or more openings is referred to as an inter-opening distance, at least one inter-opening distance is different from other inter-opening distances.

Abstract: A lighting apparatus with LED includes a metal-made main body 90; a plurality of LED chip units 1 each including an LED chip and a pair of lead terminals 42, 43 electrically connected to electrodes of the LED chip; and a dielectric layer 80 disposed between the main body 90 and each LED chip unit 1 for making electrical insulation therebetween as well as bond the same. The circuit board 20 is formed with a plurality of windows 23 through which the individual LED chip units 1 extend respectively with the lead terminals held in electrical contact with the circuit pattern of the circuit board at the circumference of the window, each of the LED chip units being thermally coupled at its bottom face with the main body 90 through the dielectric layer 80, and the heat generated in the LED chip is conducted to the main body through the dielectric layer without passing through the circuit board.

Abstract: A lighting apparatus with LED includes a metal-made main body 90; a plurality of LED chip units 1 each including an LED chip and a pair of lead terminals 42, 43 electrically connected to electrodes of the LED chip; and a dielectric layer 80 disposed between the main body 90 and each LED chip unit 1 for making electrical insulation therebetween as well as bond the same. The circuit board 20 is formed with a plurality of windows 23 through which the individual LED chip units 1 extend respectively with the lead terminals held in electrical contact with the circuit pattern of the circuit board at the circumference of the window, each of the LED chip units being thermally coupled at its bottom face with the main body 90 through the dielectric layer 80, and the heat generated in the LED chip is conducted to the main body through the dielectric layer without passing through the circuit board.

Abstract: In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.

Abstract: According to a present invention, a gate electrode and a lower electrode are formed on a semiconductor substrate and a silicide layer is formed on the gate electrode and the lower electrode. Then, a capacitor insulating film functioning as an etching stopper is formed on the entire surface and a silicide layer is formed on the entire surface. After selectively forming the silicide layer to form the upper electrode and a silicide resistance element, a layer insulating film is on the entire surface and then contact holes are formed in the layer insulating film until the capacitor insulating film is exposed. Then, the capacitor insulating film is removed to expose the gate electrode, the lower electrode, the upper electrode and the resistance element.

Abstract: A thermal oxide film is formed on a silicon substrate, a polysilicon film is formed on the thermal oxide film, and further a patterned photoresist film is formed on the polysilicon. The polysilicon film and the thermal oxide film are etched using the photoresist film as a mask so as to form a gate electrode and a gate oxide film. The photoresist film is removed therefrom, and a thermal oxide film is formed in the circumference of the gate electrode, thereby to restore a constriction formed in the gate oxide film. A part of the thermal oxide film which corresponds to the gate electrode and another part thereof which corresponds to the semiconductor substrate are removed therefrom, and a side wall nitride film which adhere to the silicon substrate is formed on a side wall of the gate electrode. Thereafter, a source and drain diffusion layers corresponding to the gate electrode are formed on the silicon substrate, thereby to form metal wiring.

Abstract: The present invention provides a manufacturing method of a semiconductor device having a single semiconductor substrate, for forming a first processing circuit portion and a second processing circuit portion having mutually different thicknesses of gate oxide films on the single semiconductor substrate including the steps of: forming a first gate oxide film over the semiconductor substrate; sequentially forming an insulating film and a first conducting layer over the entire surface of the first gate oxide film; eliminating those portions ranging from the first gate oxide film to the first conducting layer, which portions are included within an element forming region of the first processing circuit portion; and forming, only in the element forming region of the first processing circuit portion, a second gate oxide film having a thickness different from that of the first gate oxide film.

Abstract: In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.

Abstract: In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.

Abstract: The present invention provides a manufacturing method of a semiconductor device having a single semiconductor substrate, for forming a first processing circuit portion and a second processing circuit portion having mutually different thicknesses of gate oxide films on the single semiconductor substrate including the steps of: forming a first gate oxide film over the semiconductor substrate; sequentially forming an insulating film and a first conducting layer over the entire surface of the first gate oxide film; eliminating those portions ranging from the first gate oxide film to the first conducting layer, which portions are included within an element forming region of the first processing circuit portion; and forming, only in the element forming region of the first processing circuit portion, a second gate oxide film having a thickness different from that of the first gate oxide film.

Abstract: Producing method for a semiconductor device in which, for producing CMOS transistors of plural sorts, for example, dual power source transistors, having an added ROM unction, the number of times of ion implantation and resist pattern formation can be reduced to reduce the number of producing process steps. In producing a semiconductor device comprised of five sorts of MOS transistors, namely thin-film CMOS transistors (area A of FIG. 1), thick-film CMOS transistors (area B of FIG. 1) and an ROM code transistor (area C of FIG. 1), ion implantation for forming an inversion layer (13 of FIG. 1) on a channel surface of the ROM code transistor and the ion implantation for adjusting threshold value voltage of P channel of the CMOS transistor are carried out in the same process step (process (d) of FIG. 5). Also, the ion implantation for adjusting threshold value voltage of N channel of the thin-film CMOS transistor is effected using a resist pattern (4d of FIG.

Abstract: A voltage and displacement sensitive probe with an electro-optic crystal, electrically conductive transparent films and adhered to a pair of parallel surfaces on the electro-optic crystal, a transparent elastic film which circumferential portion is bonded to the frame and which is symmetric with respect to any plane through the axis thereof, a probing needle bonded at its reflective bottom surface to the central portion on the film, a holder for holding the electro-optic crystal and the transparent elastic film via frame concentrically, a lead for grounding, and electrically conductive films for connecting between the films. Displacement detection of the probing needle is based upon the change in the length of the path of the light travelling through the electro-optic crystal being reflected by the surface and travelling in reverse direction. Voltage detection of the probing needle is based upon the phase difference between the two linearly-polarized light components.

Abstract: In fabricating a buried p-channel MOS transistor using an n-type substrate, a shallow n-type diffused layer is formed by ion implantation in each of intended source and drain regions so as to become oppositely adjacent to the shallow p-type diffused layer under the gate electrode. After that p-type diffused layers to serve as source and drain are formed by ion implantation through the n-type diffused layers, and the implanted impurities are activated. In consequence, impurity concentration at the substrate surface becomes lower in the section right under each end of the gate electrode than in the gate middle sections. This measure brings about suppression of the short channel effect inherent to conventional buried-channel MOS transistors and makes it possible to shorten the physical gate length.

Abstract: A method for producing an optical module assembly includes the steps of illuminating an optical surface of an optical device included in an optical module, acquiring an image of the optical surface of the optical module, obtaining a position of an end surface of the optical fiber with respect to the optical surface of the optical device based upon the image of the optical surface, and positioning the end surface of said optical fiber at the position thus obtained. An apparatus for carrying out the method is also disclosed.

Abstract: A semiconductor device is fabricated by steps of forming, by atmospheric pressure CVD or low pressure CVD without using plasma, a first insulating layer that covers a semiconductor substrate having a protruded and recessed surface; forming, by bias plasma CVD using an electron cyclotron resonance process, a second insulating film that covers the first insulating layer; and planarizing the second insulating film by a CMP process. In this way, the time required for planarizing a surface of the semiconductor substrate by the CMP can be reduced.

Abstract: In fabricating a buried p-channel MOS transistor using an n-type substrate, a shallow n-type diffused layer is formed by ion implantation in each of intended source and drain regions so as to become oppositely adjacent to the shallow p-type diffused layer under the gate electrode. Then p-type diffused layers to serve as source and drain are formed by ion implantation through the n-type diffused layers, and the implanted impurities are activated. In consequence, impurity concentration at the substrate surface becomes lower in the section right under each end of the gate electrode than in the gate middle section. This measure brings about suppression of the short channel effect inherent to conventional buried-channel MOS transistors and makes it possible to shorten the physical gate length.

Abstract: A voltage and displacement sensitive probe with an electro-optic crystal, electrically conductive transparent films and adhered to a pair of parallel surfaces on the electro-optic crystal, a transparent elastic film which circumferential portion is bonded to the frame and which is symmetric with respect to any plane through the axis thereof, a probing needle bonded at its reflective bottom surface to the central portion on the film, a holder for holding the electro-optic crystal and the transparent elastic film via frame concentrically, a lead for grounding, and electrically conductive films for connecting between the films. Displacement detection of the probing needle is based upon the change in the length of the path of the light travelling through the electro-optic crystal being reflected by the surface and travelling in reverse direction. Voltage detection of the probing needle is based upon the phase difference between the two linearly-polarized light components.

Abstract: In a method for manufacturing a CMIS transistor, after gate electrodes are formed, deep P type impurity regions and shallow N type impurity regions are formed within both of a PMOS area and an NMOS area. Then, after sidewall insulating layers are formed on sidewalls of the gate electrodes, P type impurity ions are introduced into the PMOS area and N type impurity ions are introduced into the NMOS area.

Abstract: In a signal measuring apparatus a distance between a sample and a probe is adjusted, a voltage is applied through the sample and the probe and a signal is measured using a current flowing through the sample and the probe. That is, a current flowing through the sample and the probe is chopped by a laser beam at a prescribed frequency and is fetched into a sampling apparatus to generate a sample value of the current. The sample value is compared with a current setting value arbitrarily set in a comparator, and a reference voltage is generated according to a compared result in a control logic circuit and a D/A converter. The reference voltage is fed back to the sampling apparatus to converge the current flowing through the sample and the probe at the current setting value. Therefore, a signal of the sample is measured according to the reference voltage on condition that the current is converged at the current setting value.