Abstract: The thermostable cellobiohydrolase of the present invention is a polypeptide which has cellobiohydrolase activity at least under conditions of a temperature of 75° C. and a pH of 5.5, and which includes a polypeptide including an amino acid sequence represented by SEQ ID NO: 1, 3, 5, or 7, a polypeptide including an amino acid sequence in which one or several amino acids are deleted, substituted, or added in an amino acid sequence represented by SEQ ID NO: 1, 3, 5, or 7, or a polypeptide including an amino acid sequence having 80% or greater but less than 100% sequence identity with an amino acid sequence represented by SEQ ID NO: 1, 3, 5, or 7.

Abstract: A thermostable ?-xylosidase including a ?-xylosidase catalytic domain, the ?-xylosidase catalytic domain including: (A) a polypeptide including an amino acid sequence represented by SEQ ID NO: 1; (B) a polypeptide including an amino acid sequence in which at least one amino acid is deleted, substituted, or added in the amino acid sequence represented by SEQ ID NO: 1, and having hydrolytic activity using p-nitrophenyl-?-D-xylopyranoside as a substrate at least under conditions of a temperature of 85° C. and a pH of 6.0; or (C) a polypeptide including an amino acid sequence having at least 80% sequence identity with the amino acid sequence represented by SEQ ID NO: 1, and having hydrolytic activity using p-nitrophenyl-?-D-xylopyranoside as a substrate at least under conditions of a temperature of 85° C. and a pH of 6.0.

Abstract: A thermostable xylanase including a xylanase catalytic domain, the xylanase catalytic domain including: (A) a polypeptide comprising an amino acid sequence represented by SEQ ID NO: 1; (B) a polypeptide including an amino acid sequence in which at least one amino acid is deleted, substituted, or added in the amino acid sequence represented by SEQ ID NO: 1, and having xylanase activity at least under conditions of a temperature of 90° C. and a pH of 6.0; or (C) a polypeptide including an amino acid sequence having at least 75% sequence identity with the amino acid sequence represented by SEQ ID NO: 1, and having xylanase activity at least under conditions of a temperature of 90° C. and a pH of 6.0.

Abstract: In order to provide a semiconductor device having high ESD tolerance, a plurality of source wirings (22) are formed of metal films having the same shape and electrically connect a plurality of sources (12) to a ground voltage wiring (22a), respectively, a plurality of drain wirings (23) are formed of metal films having the same shape and electrically connect a plurality of drains (12) to an input voltage wiring (23a), respectively, and a plurality of gate wirings (21) are formed of metal films having the same shape and electrically connect a plurality of gates (11) to the ground voltage wiring (22a), respectively. Further, a back gate wiring (24) is formed of a metal film and electrically connects a back gate (14) to the ground voltage wiring (22a), and the back gate wiring (24) is separated from the source wiring (22) formed on the source (12).

Abstract: In order to provide a semiconductor device having high ESD tolerance, a semiconductor device (IC) is formed so that: a ground voltage wiring (22a) is electrically connected at one end in a wiring direction thereof to a wiring (22b) extending from a ground voltage pad used for external connection; an input voltage wiring (23a) is electrically connected at one end in a wiring direction thereof to a wiring (23b) extending from an input voltage pad used for external connection; and the one end of the ground voltage wiring (22a) and the one end of the input voltage wiring (23a) are substantially opposed to each other across a center of an NMOS transistor (10).

Abstract: A reference voltage generator has a depletion mode MOS transistor of a first conductivity type for supplying a constant current flow, and an enhancement mode MOS transistor of the first conductivity type having a diode connection to the depletion mode MOS transistor for generating a reference voltage based on a constant current supplied by the depletion mode MOS transistor. The enhancement mode MOS transistor has a mobility substantially equal to a mobility of the depletion mode MOS transistor such that the enhancement mode MOS transistor and the depletion mode MOS transistor have substantially equal temperature characteristics.

Abstract: An ESD protection circuit having a smaller area is provided. The ESD protection circuit includes: a P-type diffusion resistor 12 whose one end is connected to an input terminal 11 formed in the N-type well; a diode 14 disposed between the diffusion resistor 12 and the N-type well connected to the power supply terminal; an NMOS transistor 15 whose drain is connected to the other end of the diffusion resistor 12; and a parasitic diode formed between the power supply terminal and the ground terminal.

Abstract: A method for selectively obtaining a natural variant of an enzyme having activity includes (1) a step of detecting an ORF sequence of a protein having enzyme activity from a genome database including base sequences of metagenomic DNA of environmental microbiota; (2) a step of obtaining at least one PCR clone including the ORF sequence having a full length, a partial sequence of the ORF sequence, or a base sequence encoding an amino acid sequence which is formed by deletion, substitution, or addition of at least one amino acid residue in an amino acid sequence encoded by the ORF sequence, by performing PCR cloning on at least one metagenomic DNA of the environmental microbiota by using a primer designed based on the ORF sequence; (3) a step of determining a base sequence and an amino acid sequence which is encoded by the base sequence for each PCR clone obtained in the step (2); and (4) a step of selecting a natural variant of an enzyme having activity by measuring enzyme activity of proteins encoded by each P

Abstract: A thermostable cellobiohydrolase including a cellobiohydrolase catalytic domain, the cellobiohydrolase catalytic domain including: (A) a polypeptide including an amino acid sequence represented by SEQ ID NO: 1; (B) a polypeptide including an amino acid sequence obtained by deletion, substitution or addition of at least one amino acid of the amino acid sequence represented by SEQ ID NO: 1, and having at least a cellobiohydrolase activity under conditions of 75° C. and pH 5.5; (C) a polypeptide including an amino acid sequence having at least 85% sequence identity with the amino acid sequence represented by SEQ ID NO: 1, and having at least a cellobiohydrolase activity under conditions of 75° C. and pH 5.

Abstract: Provided is a reference voltage generator having flat temperature characteristics. The reference voltage generator includes a resistor (3) surrounding a periphery of a depletion MOS transistor (1) of a first conductivity type which is connected so as to function as a current source for causing a constant current to flow, and an enhancement MOS transistor (2) of the first conductivity type diode-connected thereto, and also includes a current source capable of being trimmed with high precision under a preset temperature environment and a diode connected in series to the current source. The reference voltage generator can operate under a given preset temperature environment because a voltage consumed in the resistor becomes approximately constant in accordance with a signal output from the diode.

Abstract: Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad (22) to a drain of an NMOS transistor of an ESD protective circuit. The first vias (16) are formed under the pad (22) only on one side of a rectangular ring-shaped intermediate metal film (17) and on another side thereof opposed to the one side. In other words, all the first vias (16) for establishing an electrical connection to the drains are present substantially directly under the pad (22). Consequently, a surge current caused by ESD and applied to the pad (22) is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protective circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device is increased.

Abstract: Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad to a drain of an NMOS transistor of an ESD protection circuit. The first via (16) is arranged directly above the drain and present substantially directly under the pad. Consequently, a surge current caused by ESD and applied to the pad is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protection circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device increases.

Abstract: An ESD protection circuit having a smaller area is provided. The ESD protection circuit includes: a P-type diffusion resistor 12 whose one end is connected to an input terminal 11 formed in the N-type well; a diode 14 disposed between the diffusion resistor 12 and the N-type well connected to the power supply terminal; an NMOS transistor 15 whose drain is connected to the other end of the diffusion resistor 12; and a parasitic diode formed between the power supply terminal and the ground terminal.

Abstract: Provided is a semiconductor device capable of suppressing latch-up generation and formed within a small area. In a minority carrier capture region, a P-type diffusion region (22), an N-type well (24), and a P-type diffusion region (25) are formed on a surface of a P-type semiconductor substrate (27). An N-type diffusion region (23) is formed on a surface of the N-type well (24). And the N-type well (24) is located between the P-type diffusion region (22) and the P-type diffusion region (25). The P-type diffusion region (22) and the P-type diffusion region (25) are each connected to a ground pad (12) not by the shortest distance but respectively through metal film wirings arranged in a diverted way.

Abstract: Provided is a memory circuit in which erroneous writing is less likely to occur at the time of power-on. A memory circuit (10) includes: a P-channel non-volatile memory element (15) for writing, to which a voltage is applied between a source and a drain thereof only during writing so as to write data; and an N-channel non-volatile memory element (16) for reading, which has a control gate and a floating gate provided in common to a control gate and a floating gate of the P-channel non-volatile memory element (15) and to which a voltage is applied to a source and a drain thereof only during reading so as to read the data.

Abstract: Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad to a drain of an NMOS transistor of an ESD protection circuit. The first via (16) is arranged directly above the drain and present substantially directly under the pad. Consequently, a surge current caused by ESD and applied to the pad is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protection circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device increases.

Abstract: Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad (22) to a drain of an NMOS transistor of an ESD protective circuit. The first vias (16) are formed under the pad (22) only on one side of a rectangular ring-shaped intermediate metal film (17) and on another side thereof opposed to the one side. In other words, all the first vias (16) for establishing an electrical connection to the drains are present substantially directly under the pad (22). Consequently, a surge current caused by ESD and applied to the pad (22) is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protective circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device is increased.

Abstract: A plant information management system comprising: a seed identification information input device; an individual plant identification information retrieval device; an individual plant identification information input device; a new seed identification information retrieval device; a storage location information retrieval device; a project database management device; a seed database management device; a project database memory device; and a seed database memory device.

Abstract: An image writing system includes: a display medium displaying an image rewritably recorded according to an external force and holding the image after the external force is removed, the display medium including a memory externally readably storing capability information on a capability of displaying an image on the display medium; and a writing apparatus applying the external force to the display medium so as to write the image into the display medium, the writing apparatus including: a reading section reading the capability information from the memory; a display-capability presenting section presenting information including the capability information, a list of images to be written, and display attributes of the respective images; an image-selection accepting section accepting a selection of an image to be written into the display medium; and a writing section applying the external force to the display medium so as to write the selected image into the display medium.

Abstract: A document processing system includes: a document management server that manages document data and an access key to access to the document data in association with each other; and an information processing unit including: a processing section; and a display detachably linked to the processing section by one of wired and wireless connection, the display holding an image of a document, the display storing the access key to access to the document data, the processing section comprising: a connection section to which the display is linked so as to read the access key from the display; a document acquisition section that acquires the document data corresponding to the access key read from the display from the document management server; and a document processing section that processes the document data acquired from the document management server.