Abstract: A semiconductor laminate film includes a silicon substrate and a semiconductor layer formed on the silicon substrate and containing silicon and germanium. The semiconductor layer having a surface roughness Rms of 1 nm or less. Further, the semiconductor layer satisfies the following relationship t?0.881×x?4.79 where t represents a thickness (nm) of the semiconductor layer, and x represents a ratio of the number of germanium atoms to a sum of the number of silicon atoms and the number of germanium atoms in the semiconductor layer. Also, the semiconductor layer being a mixed crystal semiconductor layer containing silicon and germanium.

Abstract: A method of producing a semiconductor laminate film includes forming a semiconductor layer containing silicon and germanium on a silicon substrate by a sputtering method. In the sputtering method, a film formation temperature of the semiconductor layer is less than 500° C., and a film formation pressure of the semiconductor layer ranges from 1 mTorr to 11 mTorr, or, a film formation temperature of the semiconductor layer is less than 600° C., and a film formation pressure of the semiconductor layer is equal to or more than 2 mTorr and less than 5 mTorr. The sputtering method uses a sputtering gas having a volume ratio of a hydrogen gas of less than 0.1%, and the semiconductor layer satisfies a relationship of t?0.881×x?4.79, where t represents a thickness (nm) of the semiconductor layer, and x represents a ratio of the number of germanium atoms to a sum of the number of silicon atoms and the number of germanium atoms in the semiconductor layer.

Abstract: A semiconductor laminate film includes a silicon substrate and a semiconductor layer formed on the silicon substrate and containing silicon and germanium. The semiconductor layer having a surface roughness Rms of 1 nm or less. Further, the semiconductor layer satisfies the following relationship t?0.881×x?4.79 where t represents a thickness (nm) of the semiconductor layer, and x represents a ratio of the number of germanium atoms to a sum of the number of silicon atoms and the number of germanium atoms in the semiconductor layer. Also, the semiconductor layer being a mixed crystal semiconductor layer containing silicon and germanium.

Abstract: A method of producing a semiconductor laminate film includes forming a semiconductor layer containing silicon and germanium on a silicon substrate by a sputtering method. In the sputtering method, a film formation temperature of the semiconductor layer is less than 500° C., and a film formation pressure of the semiconductor layer ranges from 1 mTorr to 11 mTorr, or, a film formation temperature of the semiconductor layer is less than 600° C., and a film formation pressure of the semiconductor layer is equal to or more than 2 mTorr and less than 5 mTorr. The sputtering method uses a sputtering gas having a volume ratio of a hydrogen gas of less than 0.1%, and the semiconductor layer satisfies a relationship of t?0.881×x?4.79, where t represents a thickness (nm) of the semiconductor layer, and x represents a ratio of the number of germanium atoms to a sum of the number of silicon atoms and the number of germanium atoms in the semiconductor layer.

Abstract: A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.

Abstract: There is offered a switching resistance RAM that is very much reduced in an occupied area and is highly integrated. Memory cells CEL11-CEL14 are formed corresponding to four intersections of word lines WL0 and WL1 and bit lines BL0 and BL1. Each of the memory cells CEL11-CEL14 are composed of a switching layer 13 formed on a surface of an N+ type Si layer 11. The switching layer 13 is electrically connected to the bit line BL0 or BL1 thereabove through an electrode 14. The switching layer 13 is composed of a SiC layer 13A stacked on the surface of the N+ type Si layer 11 and a Si oxide layer 13B stacked on the SiC layer 13A. A top surface of the Si oxide layer 13B, that is the uppermost layer of the switching layer 13, is electrically connected to the corresponding bit line BL0 or BL1.

Abstract: A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.

Abstract: There is offered a switching resistance RAM that is very much reduced in an occupied area and is highly integrated. Memory cells CEL11-CEL14 are formed corresponding to four intersections of word lines WL0 and WL1 and bit lines BL0 and BL1. Each of the memory cells CEL11-CEL14 are composed of a switching layer 13 formed on a surface of an N+ type Si layer 11. The switching layer 13 is electrically connected to the bit line BL0 or BL1 thereabove through an electrode 14. The switching layer 13 is composed of a SiC layer 13A stacked on the surface of the N+ type Si layer 11 and a Si oxide layer 13B stacked on the SiC layer 13A. A top surface of the Si oxide layer 13B, that is the uppermost layer of the switching layer 13, is electrically connected to the corresponding bit line BL0 or BL1.

Abstract: A semiconductor memory device that is configured with a Si substrate layer, a SiC layer and a Si oxide layer, including a structure in which the SiC layer is layered onto the Si substrate layer and the Si oxide layer is layered onto the SiC. Wherein, the Si oxide layer includes two or more layers whose compositional ratios of SiO2 are different in a direction of layers, and a compositional ratio of SiO2 in the. Si oxide layer that is distanced most from the SiC layer is more than other layers.

Abstract: The present invention provides an electromagnetic clutch for compressor which can align axial centers of a core ring and a rotor with high accuracy. In the present invention, since a support portion 22c for supporting a rotor 11 is provided integrally on a core ring 22, the core ring 22 can be formed coaxially with the support portion 22c, and the rotor 11 supported by the support portion 22c and the core ring 22 can be arranged on the same axial center without separate alignment. In this case, since a fixed portion 22b is engaged with an engagement portion 4c of a compressor body 4 so that movement in the radial direction is regulated, the core ring 22 is not displaced in the radial direction with respect to the compressor body 4, and the axial centers of the core ring 22 and a rotational axis 1 can be aligned with high accuracy. By this, a gap G between the core ring 22 and the rotor 11 can be made smaller, and the permeability between the core ring 22 and the rotor 11 can be improved.

Abstract: An electromagnet assembly for an electromagnetic apparatus has a ring member, a coil bobbin having an electrical wire wound a spool of the ring member, and a ring case. The ring member is disposed in an annular groove of the ring case. An opening is formed through the ring case adjacent to its closed end surface. A connector is disposed on the ring case adjacent to its closed end surface and covers the opening. A first and a second ends of the electrical wire and a first and a second ends of a lead wire are joined in, respectively the connector. A projection portion formed on the connector is inserted into the opening, and is fixed adhesively to an end surface of the ring member of the coil bobbin.

Abstract: An electromagnet assembly for an electromagnetic apparatus has a ring member, a coil bobbin having an electrical wire wound a spool of the ring member, and a ring case. The ring member is disposed in an annular groove of the ring case. An opening is formed through the ring case adjacent to its closed end surface. A connector, which is disposed on the ring case and covers the opening, includes a case having a closed shape and a bottom, and a cap closing an open end of the case. Ends of the electrical wire and ends of a lead wire are joined in the connector. A projection portion is formed around a fringe portion of a first end surface of the cap and abuts an open end surface of the case. The cap is secured fixedly to the case after the projection portion is melted.

Abstract: An electromagnet assembly for an electromagnetic apparatus has a ring member, a coil bobbin having an electrical wire wound a spool of the ring member, and a ring case. The ring member is disposed in an annular groove of the ring case. An opening is formed through the ring case adjacent to its closed end surface. A connector, which is disposed on the ring case and covers the opening, includes a case having a closed shape and a bottom, and a cap closing an open end of the case. Ends of the electrical wire and ends of a lead wire are joined in the connector. A projection portion is formed around a fringe portion of a first end surface of the cap and abuts an open end surface of the case. The cap is secured fixedly to the case after the projection portion is melted.

Abstract: An electromagnet assembly for an electromagnetic apparatus has a ring member, a coil bobbin having an electrical wire wound a spool of the ring member, and a ring case. The ring member is disposed in an annular groove of the ring case. An opening is formed through the ring case adjacent to its closed end surface. A connector, which is disposed on the ring case and covers the opening, includes a case having a closed shape and a bottom, and a cap closing an open end of the case. Ends of the electrical wire and ends of a lead wire are joined in the connector. A projection portion is formed around a fringe portion of a first end surface of the cap and abuts an open end surface of the case. The cap is secured fixedly to the case after the projection portion is melted.

Abstract: An electromagnet assembly for an electromagnetic apparatus has a ring member, a coil bobbin having an electrical wire wound a spool of the ring member, and a ring case. The ring member is disposed in an annular groove of the ring case. An opening is formed through the ring case adjacent to its closed end surface. A connector is disposed on the ring case adjacent to its closed end surface and covers the opening. A first and a second ends of the electrical wire and a first and a second ends of a lead wire are joined in, respectively the connector. A projection portion formed on the connector is inserted into the opening, and is fixed adhesively to an end surface of the ring member of the coil bobbin.

Abstract: An electromagnet assembly for an electromagnetic apparatus has a ring member, a coil bobbin having an electrical wire wound a spool of the ring member, and a ring case. The ring member is disposed in an annular groove of the ring case. An opening is formed through the ring case adjacent to its closed end surface. A connector, which is disposed on the ring case and covers the opening, includes a case having a closed shape and a bottom, and a cap closing an open end of the case. Ends of the electrical wire and ends of a lead wire are joined in the connector. A projection portion is formed around a fringe portion of a first end surface of the cap and abuts an open end surface of the case. The cap is secured fixedly to the case after the projection portion is melted.

Abstract: An ohmic electrode is formed on a cBN crystal to form a cBN semiconductor device which is used as a solid electronic element. The cBN semiconductor device may be of an n-type, a p-type or a pn junction type wherein molybdenum is deposited onto an n-type doped region of the cBN crystal or platinum is deposited onto a p-type doped region to thereby form an electrode with ohmic characteristic. The deposition of the molybdenum or the platinum is conducted by using a vapor deposition method followed by heating the attached substance at a temperature of 300.degree. C.-1100.degree. C. in an inactive gas atmosphere. The cBN semiconductor device can be used as a solid electronic element or an optoelectronic element for rectifiers, transistors, light emitting diodes and so on and integrated elements thereof.

Abstract: An ohmic electrode is formed on a cBN crystal to form a cBN semiconductor device which is used as a solid electronic element. The cBN semiconductor device may be of an n-type, a p-type or a pn junction type wherein molybdenum is deposited onto an n-type doped region of the cBN crystal or platinum is deposited onto a p-type doped region to thereby form an electrode with ohmic characteristic. The deposition of the molybdenum or the platinum is conducted by using a vapor deposition method followed by heating the attached substance at a temperature of 300.degree. C.-1100.degree. C. in an inactive gas atmosphere. The cBN semiconductor device can be used as a solid electronic element or an optoelectronic element for rectifiers, transistors, light emitting diodes and so on and integrated elements thereof.

Abstract: A photosensor for realizing an image sensor which can meet the requirements of high resolution, high operation speed and high signal-to-noise ratio is disclosed. The photosensor comprises a circuit substrate, a thin film transistor formed on the circuit substrate and an amorphous silicon photodiode formed on the substrate integral with the thin transistor between the drain and gate electrodes thereof. Also formed on the circuit substrate adjacent to the thin film transistor and photodiode are a charging switch element for coupling the photodiode to a DC power source to charge an inter-electrode capacitance of the photodiode, a charge storage capacitor charged by a channel current of the thin film transistor controlled by an inter-electrode capacitance voltage of the photodiode which varies in response to incident light after the inter-electrode capacitance has been charged, and a detecting switch element for coupling the capacitor to an output amplifier.

Abstract: An image sensor, comprising a semiconductor layer formed on at least a first region of a substrate; first electrodes arranged in line and electrically connected to the semiconductor layer of said first region; and second electrodes arranged in line and electrically connected to said semiconductor layer of said first region. The second electrodes are respectively formed as a common electrode, and each of the first electrodes, a portion of said second electrode facing the first electrode and the semiconductor layer positioned therebetween form a photo-sensing element. First wires respectively extend from said first electrodes to a second region of said substrate. An insulating layer is continuously formed on the first and second regions, covering said photo-sensing elements and the first wires as well as second wires formed in parallel on the insulating layer of said second region. The second wires are electrically connected to the first wires at through holes formed in the insulating layer.