Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

Abstract: A device for forming a conductive powder includes a reaction chamber configured to receive a conductive powder precursor gas, an inert gas and a hydrogen gas. The device further includes a radio frequency (RF) power unit configured to ignite a plasma using the inert gas and the hydrogen gas, wherein the plasma is usable to reduce, by a reduction reaction, the conductive powder precursor gas to form the conductive powder. The device further includes powder collecting cells configured to separate the conductive powder based on particle size. The device further includes a solvent inlet configured to provide a solvent to the powder collecting cells for dispersing the conductive powder in a solvent.

Abstract: A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma to form the conductive powder. The method further includes filtering the conductive powder based on particle size. The method further includes dispersing a portion of the conductive powder having a particle size below a threshold value in a fluid.

Abstract: A substrate handling device includes a substrate reception area defined by an edge. The substrate reception area includes a planar surface, wherein the edge extends upward from the planar surface. The substrate reception area further includes a plurality of contact structures extending upwards from the planar surface, wherein a first contact structure of the plurality of contact structures directly contacts a side surface of the edge, and a second contact structure of the plurality of contact structures is separated from the edge. The substrate reception area and the planar surface include a first material. At least one contact structure of the plurality of contact structures includes a second material different from the first material, and the second material has a hardness aligned to a hardness of a substrate material.

Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

Abstract: A substrate handling device includes a substrate reception area defined by an edge. The substrate reception area includes a planar surface, wherein the edge extends upward from the planar surface. The substrate reception area further includes a plurality of contact structures extending upwards from the planar surface, wherein a first contact structure of the plurality of contact structures directly contacts a side surface of the edge, a second contact structure of the plurality of contact structures separated from the edge, a shape of the first contact structure is different from a shape of the second contact structure. The substrate reception area and the planar surface include a first material. Each contact structure of the plurality of contact structures includes a second material different from the first material, and the second material has a hardness aligned to a hardness of a substrate material.

Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

Abstract: A gamma ray generator includes a rotational shaft, a plurality of holders and a plurality of gamma ray sources. The holders are connected to the rotational shaft. The gamma ray sources are disposed in the holders respectively, wherein the holders respectively have an upper portion and a lower portion connecting to the upper portion, and the gamma ray source is placed at an interface between the upper portion and the lower portion.

Abstract: A gamma ray generator includes a rotational shaft, a plurality of holders and a plurality of gamma ray sources. The holders are connected to the rotational shaft. The gamma ray sources are disposed in the holders respectively, wherein the holders respectively have an upper portion and a lower portion connecting to the upper portion, and the gamma ray source is placed at an interface between the upper portion and the lower portion.

Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate. The method includes depositing a first-side UBM layer on a first surface of the semiconductor substrate. The method includes forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the semiconductor substrate. The method includes forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.

Abstract: A substrate handling device includes a substrate reception area defined by an edge. The substrate reception area includes a planar surface, wherein the edge extends upward from the planar surface. The substrate reception area further includes a plurality of contact structures extending upwards from the planar surface, wherein a first contact structure of the plurality of contact structures directly contacts a side surface of the edge, a second contact structure of the plurality of contact structures separated from the edge, a shape of the first contact structure is different from a shape of the second contact structure. The substrate reception area and the planar surface include a first material. Each contact structure of the plurality of contact structures includes a second material different from the first material, and the second material has a hardness aligned to a hardness of a substrate material.

Abstract: A gamma ray generator includes a plate, a plurality of holes and a plurality of gamma ray sources. The plate is configured to rotate along a rotational axis. The holes are disposed in the plate, and the holes are arranged in a matrix. The gamma ray sources are respectively placed in the holes.

Abstract: A method of aligning a substrate contact material to a substrate material includes determining a hardness of a substrate material. The method further includes matching a hardness of a substrate contact material to the hardness of the substrate material. The method further includes adding the substrate contact material to a plurality of contact structures of a substrate handling device, wherein the substrate handling device comprises an edge and a planar surface, a first contact structure of the plurality of contact structures extends from the edge, and a second contact structure of the plurality of contact structures extends from the planar surface.

Abstract: A method of patterning a material layer includes the following steps. A first material layer is formed over a substrate, and the first material layer includes a first metal compound. Through a first photomask, portions of the first material layer is exposed with a gamma ray, wherein a first metal ion of the first metal compound in the portions of the first material layer is chemically reduced to a first metal grain. Other portions of the first material layer are removed to form a plurality of first hard mask patterns including the first metal grain.

Abstract: A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.

Abstract: A photomask includes a patterned photomask plate and a supporting member. The patterned photomask plate has a pattern region and a peripheral region surrounding the pattern region. The patterned photomask plate includes a plurality of openings in the pattern region. The supporting member directly abuts the patterned photomask plate and is in a peripheral region of the patterned photomask plate. The supporting member is formed from a different material than the patterned photomask plate.

Abstract: A transistor includes a silicon germanium layer, a gate stack, and source and drain features. The silicon germanium layer has a channel region. The silicon germanium layer has a first silicon-to-germanium ratio. The gate stack is disposed over the channel region of the silicon germanium layer and includes a silicon germanium oxide layer over and in contact with the channel region of the silicon germanium layer, a high-? dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-? dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio, and the second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio.

Abstract: A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature.

Abstract: A semiconductor integrated circuit (IC) including a first fin structure having a first aqueous soluble channel layer. The semiconductor IC includes a first gate structure over the first aqueous soluble channel layer, wherein the first gate structure includes a first oxide film directly contacting the first aqueous soluble channel layer, and the first oxide film includes a first material. The semiconductor IC includes a first spacer along the first gate structure, wherein a bottom surface of the first spacer is above an interface between the first oxide layer and the first aqueous soluble channel layer. The semiconductor IC includes a second fin structure having a second aqueous soluble channel layer. The semiconductor IC includes a second gate structure over the second aqueous channel layer, wherein the second gate structure includes a second oxide film directly contacting the second aqueous soluble channel layer, the second oxide film includes a second material.